Section 3.9 Hardware Description Language 109
leverage the creativity and the effort of a designer and reduce the risk of producing a
flawed design. Prototype integrated circuits are too expensive and time consuming to
build, soall modern design tools rely on a hardware description language to describe,
design, and test a circuit in software before it is ever manufactured.
A hardware description language (HDL) is a computer-based language that describes
the hardware of digital systems in a textual form. It resembles an ordinary computer
programming language, such as C, but is specifically oriented to describing hardware
structures and the behavior of logic circuits. It can be used to represent logic diagrams,
truth tables, Boolean expressions, and complex abstractions of the behavior of a digital
system. One way to view an HDL is to observe that it describes a relationship between
signals that are the inputs to a circuit and the signals that are the outputs of the circuit.
For example, an HDL description of an AND gate describes how the logic value of the
gate’s output is determined by the logic values of its inputs.
As a documentation language, an HDL is used to represent and document digital
systems in a form that can be read by both humans and computers and is suitable as
an exchange language between designers. The language content can be stored,
retrieved, edited, and transmitted easily and processed by computer software in
an efficient manner.
HDLs are used in several major steps in the design flow of an integrated circuit:
design entry, functional simulation or verification, logic synthesis, timing verification,
and fault simulation.
Design entry creates an HDL-based description of the functionality that is to be
implemented in hardware. Depending on the HDL, the description can be in a variety
of forms: Boolean logic equations, truth tables, a netlist of interconnected gates, or an
abstract behavioral model. The HDL model may also represent a partition of a larger
circuit into smaller interconnected and interacting functional units.
Logic simulation displays the behavior of a digital system through the use of a com-
puter. A simulator interprets the HDL description and either produces readable output,
such as a time-ordered sequence of input and output signal values, or displays wave-
forms of the signals. The simulation of a circuit predicts how the hardware will behave
before it is actually fabricated. Simulation detects functional errors in a design without
having to physically create and operate the circuit. Errors that are detected during a
simulation can be corrected by modifying the appropriate HDL statements. The stimu-
lus (i.e., the logic values of the inputs to a circuit) that tests the functionality of the design
is called a test bench. Thus, to simulate a digital system, the design is first described in
an HDL and then verified by simulating the design and checking it with a test bench,
which is also written in the HDL. An alternative and more complex approach relies on
formal mathematical methods to prove that a circuit is functionally correct. We will focus
exclusively on simulation.
Logic synthesis is the process of deriving a list of physical components and their
interconnections (called a netlist ) from the model of a digital system described in an
HDL. The netlist can be used to fabricate an integrated circuit or to lay out a printed
circuit board with the hardware counterparts of the gates in the list. Logic synthesis is
similar to compiling a program in a conventional high-level language. The difference is
110 Chapter 3 Gate-Level Minimization
that, instead of producing an object code, logic synthesis produces a database describing
the elements and structure of a circuit. The database specifies how to fabricate a physi-
cal integrated circuit that implements in silicon the functionality described by statements
made in an HDL. Logic synthesis is based on formal exact procedures that implement
digital circuits and addresses that part of a digital design which can be automated with
computer software. The design of today’s large, complex circuits is made possible by
logic synthesis software.
Timing verification confirms that the fabricated, integrated circuit will operate at a
specified speed. Because each logic gate in a circuit has a propagation delay, a signal
transition at the input of a circuit cannot immediately cause a change in the logic value
of the output of a circuit. Propagation delays ultimately limit the speed at which
a circuit can operate. Timing verification checks each signal path to verify that it is
not compromised by propagation delay. This step is done after logic synthesis specifies
the actual devices that will compose a circuit and before the circuit is released for
In VLSI circuit design, fault simulation compares the behavior of an ideal circuit with
the behavior of a circuit that contains a process-induced flaw. Dust and other particu-
lates in the atmosphere of the clean room can cause a circuit to be fabricated with a
fault. A circuit with a fault will not exhibit the same functionality as a fault-free circuit.
Fault simulation is used to identify input stimuli that can be used to reveal the difference
between the faulty circuit and the fault-free circuit. These test patterns will be used to
test fabricated devices to ensure that only good devices are shipped to the customer.
Test generation and fault simulation may occur at different steps in the design process,
but they are always done before production in order to avoid the disaster of producing
a circuit whose internal logic cannot be tested.
Companies that design integrated circuits use proprietary and public HDLs. In the
public domain, there are two standard HDLs that are supported by the IEEE: VHDL
and Verilog. VHDL is a Department of Defense–mandated language. (The V in VHDL
stands for the first letter in VHSIC, an acronym for very high-speed integrated circuit.)
Verilog began as a proprietary HDL of Cadence Design Systems, but Cadence trans-
ferred control of Verilog to a consortium of companies and universities known as Open
Verilog International (OVI) as a step leading to its adoption as an IEEE standard.
VHDL is more difficult to learn than Verilog. Because Verilog is an easier language than
VHDL to describe, learn, and use, we have chosen it for this book. However, the Verilog
HDL descriptions listed throughout the book are not just about Verilog, but also serve
to introduce a design methodology based on the concept of computer-aided modeling
of digital systems by means of a typical hardware description language. Our emphasis
will be on the modeling, verification, and synthesis (both manual and automated) of
Verilog models of circuits having specified behavior. The Verilog HDL was initially
approved as a standard HDL in 1995; revised and enhanced versions of the language
were approved in 2001 and 2005. We will address only those features of Verilog, includ-
ing the latest standard, that support our discussion of HDL-based design methodology
for integrated circuits.
Section 3.9 Hardware Description Language 111
The language reference manual for the Verilog HDL presents a syntax that describes
precisely the constructs that can be used in the language. In particular, a Verilog
model is composed of text using keywords, of which there are about 100. Keywords
are predefined lowercase identifiers that define the language constructs. Examples of
keywords are module, endmodule, input, output, wire, and, or, and not. For clarity,
keywords will be displayed in boldface in the text in all examples of code and wher-
ever it is appropriate to call attention to their use. Any text between two forward
slashes ( // ) and the end of the line is interpreted as a comment and will have no effect
on a simulation using the model. Multiline comments begin with / * and terminate
with * /. Blank spaces are ignored, but they may not appear within the text of a key-
word, a user-specified identifier, an operator, or the representation of a number. Ver-
ilog is case sensitive, which means that uppercase and lowercase letters are
distinguishable (e.g., not is not the same as NOT). The term module refers to the text
enclosed by the keyword pair module . . . endmodule. A module is the fundamental
descriptive unit in the Verilog language. It is declared by the keyword module and
must always be terminated by the keyword endmodule.
Combinational logic can be described by a schematic connection of gates, by a set of
Boolean equations, or by a truth table. Each type of description can be developed in
Verilog. We will demonstrate each style, beginning with a simple example of a Verilog
gate-level description to illustrate some aspects of the language.
The HDL description of the circuit of Fig. 3.35 is shown in HDL Example 3.1 . The
first line of text is a comment (optional) providing useful information to the reader. The
second line begins with the keyword module and starts the declaration (description) of
the module; the last line completes the declaration with the keyword endmodule. The
keyword module is followed by a name and a list of ports. The name ( Simple_Circuit in
this example) is an identifier. Identifiers are names given to modules, variables (e.g., a
signal), and other elements of the language so that they can be referenced in the design.
In general, we choose meaningful names for modules. Identifiers are composed of alpha-
numeric characters and the underscore (_), and are case sensitive. Identifiers must start
with an alphabetic character or an underscore, but they cannot start with a number.
Circuit to demonstrate an HDL
112 Chapter 3 Gate-Level Minimization
The port list of a module is the interface between the module and its environment.
In this example, the ports are the inputs and outputs of the circuit. The logic values of
the inputs to a circuit are determined by the environment; the logic values of the outputs
are determined within the circuit and result from the action of the inputs on the circuit.
The port list is enclosed in parentheses, and commas are used to separate elements of
the list. The statement is terminated with a semicolon (;). In our examples, all keywords
(which must be in lowercase) are printed in bold for clarity, but that is not a requirement
of the language. Next, the keywords input and output specify which of the ports are
inputs and which are outputs. Internal connections are declared as wires. The circuit in
this example has one internal connection, at terminal w1 , and is declared with the key-
word wire. The structure of the circuit is specified by a list of (predefined) primitive
gates, each identified by a descriptive keyword ( and, not, or ). The elements of the list
are referred to as instantiations of a gate, each of which is referred to as a gate instance .
Each gate instantiation consists of an optional name (such as G1, G2 , etc.) followed by
the gate output and inputs separated by commas and enclosed within parentheses. The
output of a primitive gate is always listed first, followed by the inputs. For example, the
OR gate of the schematic is represented by the or primitive, is named G3 , and has out-
put D and inputs w1 and E . ( Note : The output of a primitive must be listed first, but the
inputs and outputs of a module may be listed in any order.) The module description ends
with the keyword endmodule. Each statement must be terminated with a semicolon, but
there is no semicolon after endmodule.
It is important to understand the distinction between the terms declaration and instan-
tiation . A Verilog module is declared. Its declaration specifies the input–output behavior
of the hardware that it represents. Predefined primitives are not declared, because their
definition is specified by the language and is not subject to change by the user. Primitives
are used (i.e., instantiated), just as gates are used to populate a printed circuit board.
We’ll see that once a module has been declared, it may be used (instantiated) within a
design. Note that Simple_Circuit is not a computational model like those developed in
an ordinary programming language: The sequential ordering of the statements instanti-
ating gates in the model has no significance and does not specify a sequence of compu-
tations. A Verilog model is a descriptive model. Simple_Circuit describes what primitives
form a circuit and how they are connected. The input–output behavior of the circuit is
HDL Example 3.1 (Combinational Logic Modeled with Primitives)
// Verilog model of circuit of Figure 3.35. IEEE 1364–1995 Syntax
module Simple_Circuit (A, B, C, D, E);
A, B, C;
G1 (w1, A, B); // Optional gate instance name
G2 (E, C);
G3 (D, w1, E);
Documents you may be interested
Documents you may be interested