176 Chapter 4 Combinational Logic
Binary numbers in Verilog are specified and interpreted with the letter b preceded
by a prime. The size of the number is written first and then its value. Thus, 2′b01 speci-
fies a two-bit binary number whose value is 01. Numbers are stored as a bit pattern in
memory, but they can be referenced in decimal, octal, or hexadecimal formats with the
letters d′ o′, and h
, respectively. For example, 4′HA = 4′d10 = 4′b1010 and have the
same internal representation in a simulator. If the base of the number is not specified,
its interpretation defaults to decimal. If the size of the number is not specified, the
system assumes that the size of the number is at least 32 bits; if a host simulator has a
larger word length—say, 64 bits—the language will use that value to store unsized
numbers. The integer data type (keyword integer) is stored in a 32-bit representation.
The underscore (_) may be inserted in a number to improve readability of the code
(e.g., 16′b0101_1110_0101_0011 ). It has no other effect.
The case construct has two important variations: casex and casez . The first will treat
as don’t-cares any bits of the case expression or the case item that have logic value x or
z . The casez construct treats as don’t-cares only the logic value z , for the purpose of
detecting a match between the case expression and a case item.
The list of case items need not be complete. If the list of case items does not include
all possible bit patterns of the case expression, no match can be detected. Unlisted case
items, i.e., bit patterns that are not explicitly decoded can be treated by using the default
keyword as the last item in the list of case items. The associated statement will execute
when no other match is found. This feature is useful, for example, when there are more
possible state codes in a sequential machine than are actually used. Having a default
case item lets the designer map all of the unused states to a desired next state without
having to elaborate each individual state, rather than allowing the synthesis tool to
arbitrarily assign the next state.
The examples of behavioral descriptions of combinational circuits shown here are
simple ones. Behavioral modeling and procedural assignment statements require knowl-
edge of sequential circuits and are covered in more detail in Section 5.6.
Writing a Simple Test Bench
A test bench is an HDL program used for describing and applying a stimulus to an HDL
model of a circuit in order to test it and observe its response during simulation. Test
benches can be quite complex and lengthy and may take longer to develop than the
design that is tested. The results of a test are only as good as the test bench that is used
to test a circuit. Care must be taken to write stimuli that will test a circuit thoroughly,
exercising all of the operating features that are specified. However, the test benches
considered here are relatively simple, since the circuits we want to test implement only
combinational logic. The examples are presented to demonstrate some basic features of
HDL stimulus modules. Chapter 8 considers test benches in greater depth.
In addition to employing the always statement, test benches use the initial statement
to provide a stimulus to the circuit being tested. We use the term “ always statement”
loosely. Actually, always is a Verilog language construct specifying how the associated
statement is to execute (subject to the event control expression). The always statement
Section 4.12 HDL Models of Combinational Circuits 177
executes repeatedly in a loop. The initial statement executes only once, starting from
simulation time 0, and may continue with any operations that are delayed by a given
number of time units, as specified by the symbol #. For example, consider the initial
A = 0; B = 0;
#10 A = 1;
#20 A = 0; B = 1;
The block is enclosed between the keywords begin and end . At time 0, A and B are set
to 0. Ten time units later, A is changed to 1. Twenty time units after that (at t = 30 ), A is
changed to 0 and B to 1. Inputs specified by a three-bit truth table can be generated with
the initial block:
When the simulator runs, the three-bit vector D is initialized to 000 at time = 0. The
keyword repeat specifies a looping statement: D is incremented by 1 seven times, once
every 10 time units. The result is a sequence of binary numbers from 000 to 111.
A stimulus module has the following form:
// Declare local reg and wire identifiers.
// Instantiate the design module under test.
// Specify a stopwatch, using $finish to terminate the simulation.
// Generate stimulus, using initial and always statements.
// Display the output response (text or graphics (or both)).
A test module is written like any other module, but it typically has no inputs or outputs.
The signals that are applied as inputs to the design module for simulation are declared
in the stimulus module as local reg data type. The outputs of the design module that are
displayed for testing are declared in the stimulus module as local wire data type. The
module under test is then instantiated, using the local identifiers in its port list.
Figure 4.34 clarifies this relationship. The stimulus module generates inputs for the
design module by declaring local identifiers t_A and t_B as reg type and checks the
output of the design unit with the wire identifier t_C . The local identifiers are then used
to instantiate the design module being tested. The simulator associates the (actual) local
identifiers within the test bench, t_A, t_B , and t_C, with the formal identifiers of the
C# powerpoint - Convert PowerPoint to PDF in C#.NET
RasterEdge Visual C# .NET PowerPoint to PDF converter library control (XDoc.PowerPoint) is a mature and effective PowerPoint document converting utility. copying image from pdf to powerpoint; how to convert pdf to ppt using
178 Chapter 4 Combinational Logic
module ( A, B, C ). The association shown here is based on position in the port list, which
is adequate for the examples that we will consider. The reader should note, however,
that Verilog provides a more flexible name association mechanism for connecting ports
in larger circuits.
The response to the stimulus generated by the initial and al ways blocks will
appear in text format as standard output and as waveforms (timing diagrams) in
simulators having graphical output capability. Numerical outputs are displayed by
using Verilog system tasks . These are built-in system functions that are recognized
by keywords that begin with the symbol $ . Some of the system tasks that are useful
for display are
$display —display a one-time value of variables or strings with an end-of-line return,
$write —same as $display , but without going to next line,
$monitor —display variables whenever a value changes during a simulation run,
$time —display the simulation time,
$finish —terminate the simulation.
The syntax for $display, $write, and $monitor is of the form
Task-name (format specification, argumentlist);
The format specification uses the symbol % to specify the radix of the numbers that are
displayed and may have a string enclosed in quotes (″). The base may be binary, decimal,
hexadecimal, or octal, identified with the symbols %b, %d, %h, and %o, respectively
(%B, %D, %H, and %O are valid too). For example, the statement
$display ("%d %b %b", C, A, B);
specifies the display of C in decimal and of A and B in binary. Note that there are no
commas in the format specification, that the format specification and argument list
reg t_A, t_B;
// Stimulus generators for
// t_A and t_B go here
initial# stop_time $finish;
modulecircuit ( C , A, B )
// Description goes here
parameterstop_time= 1000 ;
circuit M ( t_C, t_A, t_B );
Interaction between stimulus and design modules
Section 4.12 HDL Models of Combinational Circuits 179
are separated by a comma, and that the argument list has commas between the
variables. An example that specifies a string enclosed in quotes may look like the
$display ("time = %0d A = %b", $time, A, B);
and will produce the display
time = 3 A = 10 B = 1
where (time = ), (A = ), and (B = ) are part of the string to be displayed. The format
specifiers %0d, %b, and %b specify the base for $time , A , and B , respectively. In display-
ing time values, it is better to use the format %0d instead of %d. This provides a display
of the significant digits without the leading spaces that %d will include. (%d will display
about 10 leading spaces because time is calculated as a 32-bit number.)
An example of a stimulus module is shown in HDL Example 4.9. The circuit to be
tested is the two-to-one-line multiplexer described in Example 4.6. The module
t_mux_2x1_df has no ports. The inputs for the mux are declared with a reg keyword and
the outputs with a wire keyword. The mux is instantiated with the local variables. The
initial block specifies a sequence of binary values to be applied during the simulation.
The output response is checked with the $monitor system task. Every time a variable in
its argument changes value, the simulator displays the inputs, output, and time. The result
of the simulation is listed under the simulation log in the example. It shows that
m_out = A when select = 1 and m_out = B when select = 0 verifying the operation of
HDL Example 4.9 (Test Bench)
// Test bench with stimulus for mux_2x1_df
parameter stop_time = 50;
mux_2x1_df M1 (t_mux_out, t_A, t_B, t_select);
// Instantiation of circuit to be tested
initial # stop_time $finish;
// Stimulus generator
t_select = 1; t_A = 0; t_B = 1;
#10 t_A = 1; t_B = 0;
#10 t_select = 0;
#10 t_A = 0; t_B = 1;
// Response monitor
// $display (″ time Select A B m_out ″);
// $monitor ( $time ,, ″ %b %b %b %b ″, t_select, t_A, t_B, t_m_out);
180 Chapter 4 Combinational Logic
Logic simulation is a fast and accurate method of verifying that a model of a
combinational circuit is correct. There are two types of verification: functional and
timing. In functional verification, we study the circuit logical operation indepen-
dently of timing considerations. This can be done by deriving the truth table of the
combinational circuit. In timing verification, we study the circuit’s operation by
including the effect of delays through the gates. This can be done by observing the
waveforms at the outputs of the gates when they respond to a given input. An exam-
ple of a circuit with gate delays was presented in Section 3.10 in HDL Example 3.3 .
We next show an HDL example that produces the truth table of a combinational
circuit. A $monitor system task displays the output caused by the given stimulus.
Acommented alternative statement having a $displ ay task would create a header
that could be used with a $monitor statement to eliminate the repetition of names
on each line of output.
The analysis of combinational circuits was covered in Section 4.3. A multilevel
circuit of a full adder was analyzed, and its truth table was derived by inspection. The
gate-level description of this circuit is shown in HDL Example 4.10. The circuit has
three inputs, two outputs, and nine gates. The description of the circuit follows the
interconnections between the gates according to the schematic diagram of Fig. 4.2 .
Thestimulus for the circuit is listed in the second module. The inputs for simulating
the circuit are specified with a three-bit reg vector D . D is equivalent to input A ,
D to input B , and D to input C . The outputs of the circuit F
as wire. The complement of F2 is named F2_b to illustrate a common industry practice
for designating the complement of a signal (instead of appending _not ). This procedure
$monitor (″ time = ″, $time ,, ″ select = %b A = %b B = %b OUT = %b ″,
t_select, t_A, t_B, t_mux_out);
// Dataflow description of two-to-one-line multiplexer
// from Example 4.6
module mux_2x1_df (m_out, A, B, select);
assign m_out = (select)? A : B;
select = 1 A = 0 B = 1 OUT = 0 time = 0
select = 1 A = 1 B = 0 OUT = 1 time = 10
select = 0 A = 1 B = 0 OUT = 0 time = 20
select = 0 A = 0 B = 1 OUT = 1 time = 30
Section 4.12 HDL Models of Combinational Circuits 181
follows the steps outlined in Fig. 4.34 . The repeat loop provides the seven binary num-
bers after 000 for the truth table. The result of the simulation generates the output
truth table displayed with the example. The truth table listed shows that the circuit is
a full adder.
HDL Example 4.10 (Gate-Level Circuit)
// Gate-level description of circuit of Fig. 4.2
module Circuit_of_Fig_4_2 (A, B, C, F1, F2);
input A, B, C;
output F1, F2;
wire T1, T2, T3, F2_b, E1, E2, E3;
or g1 (T1, A, B, C);
and g2 (T2, A, B, C);
and g3 (E1, A, B);
and g4 (E2, A, C);
and g5 (E3, B, C);
or g6 (F2, E1, E2, E3);
not g7 (F2_b, F2);
and g8 (T3, T1, F2_b);
or g9 (F1, T2, T3);
// Stimulus to analyze the circuit
reg [2: 0] D;
wire F1, F2;
Circuit_of_Fig_4_2 (D, D, D, F1, F2);
D = 3’b000;
repeat (7) #10 D = D 1 1’b1;
$monitor (″ ABC = %b F1 = %b F2 =%b ″, D, F1, F2);
Simulation log: ABC = 000 F1 = 0 F2 =0
ABC = 001 F1 = 1 F2 =0 ABC = 010 F1 = 1 F2 =0
ABC = 011 F1 = 0 F2 =1 ABC = 100 F1 = 1 F2 =0
ABC = 101 F1 = 0 F2 =1 ABC = 110 F1 = 0 F2 =1
ABC = 111 F1 = 1 F2 =1
182 Chapter 4 Combinational Logic
(Answers to problems marked with * appear at the end of the text. Where appropriate, a logic
design and its related HDL modeling problem are cross-referenced.)
4.1 Consider the combinational circuit shown in Fig. P4.1 . (HDL—see Problem 4.49.)
(a)* Derive the Boolean expressions for T
. Evaluate the outputs F
as a function of the four inputs.
(b) List the truth table with 16 binary combinations of the four input variables. Then list
the binary values for T
and outputs F
in the table.
(c) Plot the output Boolean functions obtained in part (b) on maps and show that the
simplified Boolean expressions are equivalent to the ones obtained in part (a).
4.2* Obtain the simplified Boolean expressions for output F and G in terms of the input
variables in the circuit of Fig. P4.2 .
4.3 For the circuit shown in Fig. 4.26 (Section 4.11),
(a) Write the Boolean functions for the four outputs in terms of the input variables.
(b)* If the circuit is described in a truth table, how many rows and columns would there
be in the table?
4.4 Design a combinational circuit with three inputs and one output.
(a)* The output is 1 when the binary value of the inputs is less than 3. The output is 0 otherwise.
(b) The output is 1 when the binary value of the inputs is an even number.
Documents you may be interested
Documents you may be interested