186 Chapter 4 Combinational Logic
4.29* Design a four-input priority encoder with inputs as in Table 4.8 , but with input D
the highest priority and input D
the lowest priority.
4.30 Specify the truth table of an octal-to-binary priority encoder. Provide an output V to in-
dicate that at least one of the inputs is present. The input with the highest subscript num-
ber has the highest priority. What will be the value of the four outputs if inputs D
are 1 at the same time? (HDL—see Problem 4.65.)
4.31 Construct a 16 × 1 multiplexer with two 8 × 1 and one 2 × 1 multiplexers. Use block dia-
grams. (HDL—see Problem 4.67.)
4.32 Implement the following Boolean function with a multiplexer (HDL—see Problem 4.46):
(a) F1A, B, C, D2 = ∑10, 2, 5, 8, 10, 142
(b) F1A, B, C, D2 =12, 6, 112
4.33 Implement a full adder with two 4 × 1 multiplexers.
4.34 An 8 × 1 multiplexer has inputs A , B , and C connected to the selection inputs S
, respectively. The data inputs I
are as follows:
= 0; I
= 1; I
= D ; and I
= D ’.
= 0; I
= 1; I
= D ; and I
= D ’.
Determine the Boolean function that the multiplexer implements.
4.35 Implement the following Boolean function with a 4 × 1 multiplexer and external gates.
1A, B, C, D2 = ∑11, 3, 4, 11, 12, 13, 14, 152
1A, B, C, D2 = ∑11, 2, 5, 7, 8, 10, 11, 13, 152
Connect inputs A and B to the selection lines. The input requirements for the four data
lines will be a function of variables C and D . These values are obtained by expressing F as
a function of C and D for each of the four cases when AB = 00, 01, 10, and 11. These func-
tions may have to be implemented with external gates. (HDL—see Problem 4.47.)
4.36 Write the HDL gate-level description of the priority encoder circuit shown in Fig. 4.23 .
(HDL—see Problem 4.45.)
4.37 Write the HDL gate-level hierarchical description of a four-bit adder–subtractor for un-
signed binary numbers. The circuit is similar to Fig. 4.13 but without output V . You can
instantiate the four-bit full adder described in HDL Example 4.2. (HDL—see Problems
4.13 and 4.40.)
4.38 Write the HDL dataflow description of a quadruple 2-to-1-line multiplexer with enable
(see Fig. 4.26 ).
4.39* Write an HDL behavioral description of a four-bit comparator with a six-bit output Y
Bit 5 of Y is for “equals,” bit 4 for “not equal to,” bit 3 for “greater than,” bit 2 for “less
than,” bit 1 for “greater than or equal,” and bit 0 for “less than or equal to.”
4.40 Using the conditional operator (?:), write an HDL dataflow description of a four-bit adder–
subtractor of unsigned numbers. (See Problems 4.13 and 4.37.)
4.41 Repeat problem 4.40 using an always statement.
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4.42 (a) Write an HDL gate-level description of the BCD-to-excess-3 converter circuit shown
in Fig. 4.4 (see Problem 4.22).
(b) Write a dataflow description of the BCD-to-excess-3 converter using the Boolean
expressions listed in Fig. 4.3 .
(c)* Write an HDL behavioral description of a BCD-to-excess-3 converter.
(d) Write a test bench to simulate and test the BCD-to-excess-3 converter circuit in order
to verify the truth table. Check all three circuits.
4.43 Explain the function of the circuit specified by the following HDL description:
module Prob4_43 (A, B, S, E, Q);
input [1:0] A, B;
input S, E;
output [1:0] Q;
assign Q = E ? (S ? A : B) : 'bz;
4.44 Using a case statement, write an HDL behavioral description of a eight-bit arithmetic-
logic unit (ALU). The circuit has a three-bit select bus (Sel), sixteen-bit input datapaths
(A[15:0] and B[15:0]), an eight-bit output datapath (y[15:0]), and performs the arithmetic
and logic operations listed below.
y = 8′b0
y = A & B
y = A | B
y = A ^ B
Bitwise exclusive OR
y = ~ A
y = A - B
y = A + B
Add (Assume A and B are unsigned)
y = 8′hFF
4.45 Write an HDL behavioral description of a four-input priority encoder. Use a four-bit vector
for the D inputs and an always block with if–else statements. Assume that input D  has
the highest priority (see Problem 4.36).
4.46 Write a Verilog dataflow description of the logic circuit described by the Boolean function
in Problem 4.32.
4.47 Write a Verilog dataflow description of the logic circuit described by the Boolean function
in Problem 4.35.
4.48 Develop and modify the eight-bit ALU specified in Problem 4.44 so that it has three-state
output controlled by an enable input, En . Write a test bench and simulate the circuit.
4.49 For the circuit shown in Fig. P4.1,
(a) Write and verify a gate-level HDL model of the circuit.
(b) Compare your results with those obtained for Problem 4.1.
4.50 Using a case statement, develop and simulate a behavioral model of
(a)* The 8, 4, –2, –1 to BCD code converter described in Problem 4.8(a).
(b) The 8, 4, –2, –1 to Gray code converter described in Problem 4.8(b).
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188 Chapter 4 Combinational Logic
4.51 Develop and simulate a behavioral model of the ABCD-to-seven-segment decoder
described in Problem 4.9.
4.52 Using a continuous assignment, develop and simulate a dataflow model of
(a) The four-bit incrementer described in Problem 4.11(a).
(b) The four-bit decrementer described in Problem 4.11(b).
4.53 Develop and simulate a structural model of the decimal adder shown in Fig. 4.14 .
4.54 Develop and simulate a behavioral model of a circuit that generates the 9’s complement of
(a) a BCD digit (see Problem 4.18(a)).
(b) a Gray-code digit (see Problem 4.18(b).)
4.55 Construct a hierarchical model of the BCD adder–subtractor described in Problem 4.19.
The BCD adder and the 9’s complementer are to be described as behavioral models in
separate modules, and they are to be instantiated in a top-level module.
4.56* Write a continuous assignment statement that compares two 4-bit numbers to check if
their bit patterns match. The variable to which the assignment is made is to equal 1 if the
numbers match and 0 otherwise.
4.57* Develop and verify a behavioral model of the four-bit priority encoder described in
4.58 Write a Verilog model of a circuit whose 32-bit output is formed by shifting its 32-bit input
three positions to the right and filling the vacant positions with the bit that was in the MSN
before the shift occurred (shift arithmetic right).Write a Verilog model of a circuit whose
32-bit output is formed by shifting its 32-bit input three positions to the left and filling the
vacant positions with 0 (shift logical left).
4.59 Write a Verilog model of a BCD-to-decimal decoder using the unused combinations of
the BCD code as don’t-care conditions (see Problem 4.24).
4.60 Using the port syntax of the IEEE 1364-2001 standard, write and verify a gate-level model
of the four-bit even parity checker shown in Fig. 3.34 .
4.61 Using continuous assignment statements and the port syntax of the IEEE 1364-2001 standard,
write and verify a gate-level model of the four-bit even parity checker shown in Fig. 3.34 .
4.62 Write and verify a gate-level hierarchical model of the circuit described in Problem 4.25.
4.63 Write and verify a gate-level hierarchical model of the circuit described in Problem 4.26.
4.64 Write and verify a Verilog model of the octal-to-binary circuit described in Problem 4.30.
4.65 Write a hierarchical gate-level model of the multiplexer described in Problem 4.31.
B hasker , J. 1997. A Verilog HDL Primer. Allentown, PA: Star Galaxy Press.
B hasker , J. 1998. Verilog HDL Synthesis. Allentown, PA: Star Galaxy Press.
C iletti , M. D. 1999. Modeling, Synthesis, and Rapid Prototyping with Verilog HDL. Upper
Saddle River, NJ: Prentice Hall.
D ietmeyer , D. L. 1988. Logic Design of Digital Systems, 3rd ed. Boston: Allyn Bacon.
Web Search Topics 189
G ajski , D. D. 1997. Principles of Digital Design. Upper Saddle River, NJ: Prentice Hall.
H ayes , J. P. 1993. Introduction to Digital Logic Design. Reading, MA: Addison-Wesley.
K atz , R. H. 2005. Contemporary Logic Design. Upper Saddle River, NJ: Pearson Prentice Hall.
M ano , M. M. and C. R. K ime . 2007. Logic and Computer Design Fundamentals, 4th ed.
Upper Saddle River, NJ: Prentice Hall.
N elson, V. P., H. T. N agle , J. D. I rwin , and B. D. C arroll . 1995. Digital Logic Circuit
Analysis and Design. Englewood Cliffs, NJ: Prentice Hall.
P alnitkar , S. 1996. Verilog HDL: A Guide to Digital Design and Synthesis. Mountain View,
CA: SunSoft Press (a Prentice Hall title).
R oth , C. H. 2009. Fundamentals of Logic Design, 6th ed. St. Paul, MN: West.
T homas , D. E. and P. R. M oorby . 2002. The Verilog Hardware Description Language,
5thed. Boston: Kluwer Academic Publishers.
W akerly , J. F. 2005. Digital Design: Principles and Practices, 4th ed. Upper Saddle River,
NJ: Prentice Hall.
WEB SEARCH TOPICS
Synchronous Sequential Logic
Hand-held devices, cell phones, navigation receivers, personal computers, digital cameras,
personal media players, and virtually all electronic consumer products have the ability to
send, receive, store, retrieve, and process information represented in a binary format. The
technology enabling and supporting these devices is critically dependent on electronic
components that can store information, i.e., have memory. This chapter examines the
operation and control of these devices and their use in circuits and enables you to better
understand what is happening in these devices when you interact with them. The digital
circuits considered thus far have been combinational—their output depends only and
immediately on their inputs—they have no memory, i.e., dependence on past values of
their inputs. Sequential circuits, however, act as storage elements and have memory. They
can store, retain, and then retrieve information when needed at a later time. Our treatment
will distinguish sequential logic from combinational logic.
5.2 SEQUENTIAL CIRCUITS
A block diagram of a sequential circuit is shown in Fig. 5.1 . It consists of a combinational
circuit to which storage elements are connected to form a feedback path. The storage
elements are devices capable of storing binary information. The binary information
stored in these elements at any given time defines the state of the sequential circuit at
that time. The sequential circuit receives binary information from external inputs that,
together with the present state of the storage elements, determine the binary value of
the outputs. These external inputs also determine the condition for changing the state
Section 5.2 Sequential Circuits 191
in the storage elements. The block diagram demonstrates that the outputs in a sequen-
tial circuit are a function not only of the inputs, but also of the present state of the stor-
age elements. The next state of the storage elements is also a function of external inputs
and the present state. Thus, a sequential circuit is specified by a time sequence of inputs,
outputs, and internal states . In contrast, the outputs of combinational logic depend only
on the present values of the inputs.
There are two main types of sequential circuits, and their classification is a function of
the timing of their signals. A synchronous sequential circuit is a system whose behavior
canbe defined from the knowledge of its signals at discrete instants of time. The behavior
of an asynchronous sequential circuit depends upon the input signals at any instant of time
and the order in which the inputs change. The storage elements commonly used in asyn-
chronous sequential circuits are time-delay devices. The storage capability of a time-delay
device varies with the time it takes for the signal to propagate through the device. In prac-
tice, the internal propagation delay of logic gates is of sufficient duration to produce the
needed delay, so that actual delay units may not be necessary. In gate-type asynchronous
systems, the storage elements consist of logic gates whose propagation delay provides the
required storage. Thus, an asynchronous sequential circuit may be regarded as a combina-
tional circuit with feedback. Because of the feedback among logic gates, an asynchronous
sequential circuit may become unstable at times. The instability problem imposes many
difficulties on the designer. These circuits will not be covered in this text.
A synchronous sequential circuit employs signals that affect the storage elements at
only discrete instants of time. Synchronization is achieved by a timing device called a
clock generator, which provides a clock signal having the form of a periodic train of clock
pulses . The clock signal is commonly denoted by the identifiers clock and clk . The clock
pulses are distributed throughout the system in such a way that storage elements are
affected only with the arrival of each pulse. In practice, the clock pulses determine when
computational activity will occur within the circuit, and other signals (external inputs
and otherwise) determine what changes will take place affecting the storage elements
and the outputs. For example, a circuit that is to add and store two binary numbers would
compute their sum from the values of the numbers and store the sum at the occurrence
of a clock pulse. Synchronous sequential circuits that use clock pulses to control storage
elements are called clocked sequential circuits and are the type most frequently encoun-
tered in practice. They are called synchronous circuits because the activity within the
circuit and the resulting updating of stored values is synchronized to the occurrence of
Block diagram of sequential circuit
192 Chapter 5 Synchronous Sequential Logic
clock pulses. The design of synchronous circuits is feasible because they seldom manifest
instability problems and their timing is easily broken down into independent discrete
steps, each of which can be considered separately.
The storage elements (memory) used in clocked sequential circuits are called flip-
flops. A flip-flop is a binary storage device capable of storing one bit of information. In
a stable state, the output of a flip-flop is either 0 or 1. A sequential circuit may use many
flip-flops to store as many bits as necessary. The block diagram of a synchronous clocked
sequential circuit is shown in Fig. 5.2 . The outputs are formed by a combinational logic
function of the inputs to the circuit or the values stored in the flip-flops (or both). The
value that is stored in a flip-flop when the clock pulse occurs is also determined by the
inputs to the circuit or the values presently stored in the flip-flop (or both). The new
value is stored (i.e., the flip-flop is updated) when a pulse of the clock signal occurs.
Prior to the occurrence of the clock pulse, the combinational logic forming the next
value of the flip-flop must have reached a stable value. Consequently, the speed at
which the combinational logic circuits operate is critical. If the clock (synchronizing)
pulses arrive at a regular interval, as shown in the timing diagram in Fig. 5.2 , the com-
binational logic must respond to a change in the state of the flip-flop in time to be
updated before the next pulse arrives. Propagation delays play an important role in
determining the minimum interval between clock pulses that will allow the circuit to
operate correctly. Achange in state of the flip-flops is initiated only by a clock pulse
transition—for example, when the value of the clock signals changes from 0 to 1. When
a clock pulse is not active, the feedback loop between the value stored in the flip-flop
and the value formed at the input to the flip-flop is effectively broken because the flip-
flop outputs cannot change even if the outputs of the combinational circuit driving their
inputs change in value. Thus, the transition from one state to the next occurs only at
predetermined intervals dictated by the clock pulses.
Synchronous clocked sequential circuit
(a) Block diagram
(b) Timing diagram of clock pulses
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