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LM12L458
www.ti.com
SNAS085B– JULY1999– REVISEDMARCH2013
Figure8. TheSpecificCaseoftheV
REF
OperatingRangeforV
A
+=3.3V
TransferCharacteristicandStaticErrors
Figure9. TransferCharacteristic
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LM12L458
SNAS085B– JULY1999– REVISEDMARCH2013
www.ti.com
Figure10. SimplifiedErrorCurvevs.OutputCodewithoutAuto-CalibrationorAuto-ZeroCycles
Figure11. SimplifiedErrorCurvevs.OutputCodeafterAuto-CalibrationCycle
Figure12. OffsetorZeroErrorVoltage
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LM12L458
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SNAS085B– JULY1999– REVISEDMARCH2013
TypicalPerformanceCharacteristics
Thefollowingcurvesapplyfor12-bit+signmodeafterauto-calibrationwithV
A
+=V
D
+=+3.3V,V
REF+
=+2.5V,V
REF
=0V,T
A
=25°C,andf
CLK
=6MHzunlessotherwisespecified.Theperformancefor8-bit+signand“watchdog” modesisequaltoor
betterthanshown.
(1)
LinearityErrorChange
LinearityErrorChange
vs.ClockFrequency
vs.Temperature
Figure13.
Figure14.
LinearityErrorChange
LinearityErrorChange
vs.ReferenceVoltage
vs.SupplyVoltage
Figure15.
Figure16.
Full-ScaleErrorChange
Full-ScaleErrorChange
vs.ClockFrequency
vs.Temperature
Figure17.
Figure18.
(1) WiththetestconditionforV
REF
=V
REF+
-V
REF-
givenas+2.5V,the12-bitLSBis305µ Vandthe8-bit/“Watchdog” ” LSBis4.88mV.
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LM12L458
SNAS085B– JULY1999– REVISEDMARCH2013
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TypicalPerformanceCharacteristics (continued)
Thefollowingcurvesapplyfor12-bit+signmodeafterauto-calibrationwithV
A
+=V
D
+=+3.3V,V
REF+
=+2.5V,V
REF
=0V,T
A
=25°C,andf
CLK
=6MHzunlessotherwisespecified.Theperformancefor8-bit+signand“watchdog” modesisequaltoor
betterthanshown.
(1)
Full-ScaleErrorChange
Full-ScaleError
vs.ReferenceVoltage
vs.SupplyVoltage
Figure19.
Figure20.
ZeroErrorChange
ZeroErrorChange
vs.ClockFrequency
vs.Temperature
Figure21.
Figure22.
ZeroErrorChange
ZeroErrorChange
vs.ReferenceVoltage
vs.SupplyVoltage
Figure23.
Figure24.
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LM12L458
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SNAS085B– JULY1999– REVISEDMARCH2013
TypicalPerformanceCharacteristics (continued)
Thefollowingcurvesapplyfor12-bit+signmodeafterauto-calibrationwithV
A
+=V
D
+=+3.3V,V
REF+
=+2.5V,V
REF
=0V,T
A
=25°C,andf
CLK
=6MHzunlessotherwisespecified.Theperformancefor8-bit+signand“watchdog” modesisequaltoor
betterthanshown.
(1)
AnalogSupplyCurrent
DigitalSupplyCurrent
vs.Temperature
vs.ClockFrequency
Figure25.
Figure26.
DigitalSupplyCurrent
vs.Temperature
Figure27.
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LM12L458
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www.ti.com
TimingDiagrams
V
A
+=V
D
+=+3.3V,t
R
=t
F
=3ns,C
L
=100pFfortheINT,DMARQ,D0– D15outputs.
Figure28. MultiplexedDataBus
1,3:CSorAddressvalidtoALElowset-uptime.
11:WRpulsewidth
2,4:CSorAddressvalidtoALElowholdtime.
12:WRhightonextALEhigh
5:ALEpulsewidth
13:WRhightonextWRorRDlow
6:RDhightonextALEhigh
14:DatavalidtoWRhighset-uptime
7:ALElowtoRDlow
15:DatavalidtoWRhighholdtime
8:RDpulsewidth
16:RDlowtodatabusoutofTRI-STATE
9:RDhightonextRDorWRlow
17:RDhightoTRI-STATE
10:ALElowtoWRlow
18:RDlowtodatavalid(accesstime)
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Figure29. Non-MultiplexedDataBus(ALE=1)
8:RDpulsewidth
16:RDlowtodatabusoutofTRI-STATE
9:RDhightonextRDorWRlow
17:RDhightoTRI-STATE
11:WRpulsewidth
18:RDlowtodatavalid(accesstime)
13:WRhightonextWRorRDlow
19:AddressinvalidfromRDorWRhigh(holdtime)
14:DatavalidtoWRhighset-uptime
20:CSloworaddressvalidtoRDlow
15:DatavalidtoWRhighholdtime
21:CSloworaddressvalidtoWRlow
V
A
+=V
D
+=+3.3V,t
R
=t
F
=3ns,C
L
=100pFfortheINT,DMARQ,D0– D15outputs.
Figure30. InterruptandDMARQ
22:INThighfrom RDlow
23:DMARQlowfromRDlow
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PINDESCRIPTIONS
V
A
+,V
D
+Analoganddigitalsupplyvoltagepins.TheLM12L458'ssupplyvoltageoperatingrangeis+3.0Vto
+5.5V.AccuracyisensuredonlyifV
A
+andV
D
+areconnectedtothesamepowersupply.Eachpin
shouldhaveaparallelcombinationof10
μ
F(electrolyticortantalum)and0.1
μ
F(ceramic)bypass
capacitorsconnectedbetweenitandground.
D0– D15Theinternaldatainput/outputTRI-STATEbuffersareconnectedtothesepins.Thesebuffersare
designedtodrivecapacitiveloadsof100pForless.Externalbuffersarenecessaryfordrivinghigherload
capacitances.Thesepinsallowstheuserameansofinstructioninputanddataoutput.Withalogichigh
appliedtotheBW pin,datalinesD8– D15areplacedinahighimpedancestateanddatalinesD0– D7are
usedforinstructioninputanddataoutputwhentheLM12L458isconnectedtoan8-bitwidedatabus.A
logiclow ontheBW pinallowstheLM12L458toexchangeinformationovera16-bitwidedatabus.
RD
InputfortheactivelowREADbuscontrolsignal.Thedatainput/outputTRI-STATEbuffers,asselectedby
thelogicsignalappliedtotheBW pin,areenabledwhenRDandCSarebothlow.Thisallowsthe
LM12L458totransmitinformationontothedatabus.
WR
InputfortheactivelowWRITEbuscontrolsignal.Thedatainput/outputTRI-STATEbuffers,asselected
bythelogicsignalappliedtotheBW pin,areenabledwhenWRandCSarebothlow.Thisallowsthe
LM12L458toreceiveinformationfromthedatabus.
CS
InputfortheactivelowChipSelectcontrolsignal.Alogiclowshouldbeappliedtothispinonlyduringa
READorWRITEaccesstotheLM12L458.TheinternalclockingishaltedandconversionstopswhileChip
Selectislow.ConversionresumeswhentheChipSelectinputsignalreturnshigh.
ALE AddressLatchEnableinput.Itisusedinsystemscontainingamultiplexeddatabus.WhenALEis
assertedhigh,theLM12L458acceptsinformationonthedatabusasavalidaddress.Ahigh-to-low
transitionwilllatchtheaddressdataonA0– A4andthelogicstateontheCSinput.Anychangeson
A0– A4andCSwhileALEislowwillnotaffecttheLM12L458.SeeFigure28.Whenanon-multiplexedbus
isused,ALEiscontinuouslyassertedhigh.SeeFigure29.
CLK Externalclockinputpin.TheLM12L458operateswithaninputclockfrequencyintherangeof0.05MHz
to8MHz.
A0– A4TheLM12L458'saddresslines.Theyareusedtoaccessallinternalregisters,ConversionFIFO,and
InstructionRAM.
SYNCSynchronizationinput/output.Whenusedasanoutput,itisdesignedtodrivecapacitiveloadsof100pF
orless.Externalbuffersarenecessaryfordrivinghigherloadcapacitances.SYNCisaninputifthe
Configurationregister's“I/OSelect” bitislow .ArisingedgeonthispincausestheinternalS/Htoholdthe
inputsignal.Thenextrisingclockedgeeitherstartsaconversionormakesacomparisontoa
programmablelimitdependingonwhichfunctionisrequestedbyaprogramminginstruction.Thispinwill
beanoutputif“I/OSelect” issethigh.TheSYNCoutputgoeshighwhenaconversionoracomparison
isstartedandlowwhencompleted.(SeeCONFIGURATIONREGISTER).Aninternalresetafterpoweris
firstappliedtotheLM12L458automaticallysetsthispinasaninput.
BW
BusWidthinputpin.ThisinputallowstheLM12L458tointerfacedirectlywitheitheran8-or16-bitdata
bus.Alogichighsetsthewidthto8bitsandplacesD8– D15inahighimpedancestate.Alogiclowsets
thewidthto16bits.
INT
Activelowinterruptoutput.Thisoutputisdesignedtodrivecapacitiveloadsof100pForless.External
buffersarenecessaryfordrivinghigherloadcapacitances.Aninterruptsignalisgeneratedanytimea
non-maskedinterruptconditiontakesplace.Thereareeightdifferentconditionsthatcancausean
interrupt.AnyinterruptisresetbyreadingtheInterruptStatusregister.(SeeINTERRUPTS)
DMARQActivehighDirectMemoryAccessRequestoutput.Thisoutputisdesignedtodrivecapacitiveloadsof
100pForless.Externalbuffersarenecessaryfordrivinghigherloadcapacitances.Itgoeshighwhenever
thenumberofconversionresultsintheconversionFIFOequalsaprogrammablevaluestoredinthe
InterruptEnableregister.ItreturnstoalogiclowwhentheFIFOisempty.
GND Groundconnection.Itshouldbeconnectedtoalowresistanceandinductanceanaloggroundreturnthat
connectsdirectlytothesystempowersupplyground.
IN0– IN7Thesearetheeightanaloginputs.AgivenchannelisselectedthroughtheinstructionRAM.Anyofthe
channelscanbeconfiguredasanindependentsingle-endedinput.Anypairofchannels,whetheradjacent
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ornon-adjacent,canoperateasafullydifferentialpair.
V
REF
Thisisthenegativereferenceinput.TheLM12L458operateswith0V
V
REF
V
REF+
.Thispinshouldbe
bypassedtogroundwithaparallelcombinationof10
μ
Fand0.1
μ
F(ceramic)capacitors.
V
REF+
Positivereferenceinput.TheLM12L458operatewith0V
V
REF+
V
A
+.Thispinshouldbebypassedto
groundwithaparallelcombinationof10
μ
Fand0.1
μ
F(ceramic)capacitors.
N.C. Thisisanoconnectpin.
FUNCTIONALDESCRIPTION
TheLM12L458isamulti-functionalDataAcquisitionSystemthatincludesafullydifferential12-bit-plus-signself-
calibrating analog-to-digital converter (ADC) with a two's-complement output format, an 8-channel analog
multiplexer,afirst-in-first-out(FIFO)registerthatcanstore32conversionresults,andanInstructionRAMthat
canstoreasmanyaseightinstructionstobesequentiallyexecuted.Allofthiscircuitryoperatesononlyasingle
+3.3Vpowersupply.
TheLM12L458hasthreemodesofoperation:
1. 12-bit+signwithcorrection
2. 8-bit+signwithoutcorrection
3. 8-bit+signcomparisonmode(“watchdog” mode)
The fully differential 12-bit-plus-sign ADC uses a charge redistribution topology that includes calibration
capabilities.Chargere-distributionADCsuseacapacitorladderinplaceofaresistorladdertoformaninternal
DAC.TheDACisusedbyasuccessiveapproximationregistertogenerateintermediatevoltagesbetweenthe
voltages applied to V
REF
and V
REF+
.Theseintermediate voltagesare comparedagainst the sampledanalog
inputvoltageaseachbitisgenerated.ThenumberofintermediatevoltagesandcomparisonsequalstheADC's
resolution.Thecorrectionofeachbit'saccuracyisaccomplishedbycalibratingthecapacitorladderusedinthe
ADC.
Twodifferentcalibrationmodesareavailable;onecompensatesforoffsetvoltage,orzeroerror,whiletheother
correctsbothoffseterrorandtheADC'slinearityerror.
Whencorrectingoffsetonly,theoffseterrorismeasuredonceandacorrectioncoefficientiscreated.Duringthe
fullcalibration,theoffseterrorismeasuredeighttimes,averaged,andacorrectioncoefficientiscreated.After
completionofeither calibrationmode,theoffset correctioncoefficientis stored inan internal offset correction
register.
TheLM12L458's overall linearitycorrectionis achieved by correcting the internal DAC'scapacitor mismatch.
Each capacitor is compared eight times against all remaining smaller value capacitors and any errors are
averaged.Acorrectioncoefficientisthencreatedandstoredinoneofthethirteeninternal linearitycorrection
registers. An internal state machine, using patterns stored in an internal 16 x 8-bit ROM, executes each
calibrationalgorithm.
Oncecalibrated,aninternalarithmeticlogicunit(ALU)usestheoffsetcorrectioncoefficientandthe13linearity
correctioncoefficientstoreducetheconversion'soffseterrorandlinearityerror,inthebackground,duringthe12-
bit+signconversion.The8-bit+signconversionandcomparisonmodesuseonlytheoffsetcoefficient.The8-
bit+signmodeperformsaconversioninlessthanhalfthetimeusedbythe12-bit+signconversionmode.
TheLM12L458's “watchdog” ” mode is usedto monitor a single-ended or differential signal's amplitude. Each
sampledsignal hastwolimits.Aninterruptcanbegeneratediftheinputsignalisaboveorbeloweitherofthe
two limits. This allows interrupts to be generated when analog voltage inputs are “inside the window” ” or,
alternatively, “outside the window”. After a “watchdog” ” mode interrupt, the processor can then request a
conversionontheinputsignalandreadthesignal'smagnitude.
Theanaloginputmultiplexercanbeconfiguredforanycombinationofsingle-endedorfullydifferentialoperation.
Each input is referenced to ground when a multiplexer channel operates in the single-ended mode. Fully
differentialanaloginputchannelsareformedbypairinganytwochannelstogether.
TheLM12L458'sinternalS/Hisdesignedtooperateatitsminimumacquisitiontime(1.5
μ
s,12bits)whenthe
sourceimpedance,R
S
,is
80
Ω
(f
CLK
6MHz).When80
Ω
<R
S
5.56k
Ω
,theinternalS/H'sacquisitiontime
canbeincreasedtoamaximum of6.5
μ
s(12bits,f
CLK
=6MHz).SeeINSTRUCTIONRAM (InstructionRAM
“00”)Bits12– 15formoreinformation.
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Microprocessoroverhead is reduced throughtheuse of the internal conversionFIFO. Thirty-two consecutive
conversions can be completed and stored in the FIFO without any microprocessor intervention. The
microprocessorcan,atanytime,interrogatetheFIFOandretrieveitscontents.ItcanalsowaitfortheLM12L458
toissueaninterruptwhentheFIFOisfullorafteranynumber(
32)ofconversionshavebeenstored.
Conversion sequencing, internal timer interval, multiplexer configuration, and many other operations are
programmedandsetintheInstructionRAM.
A diagnostic mode is available that allows verification of the LM12L458's operation. This mode internally
connectsthevoltagespresentattheV
REF+
,V
REF
,andGNDpinstotheinternalV
IN+
andV
IN
S/Hinputs.This
modeisactivatedbysettingtheDiagnosticbit(Bit11)intheConfigurationregistertoa“1”.Moreinformation
concerningthismodeofoperationcanbefoundinCONFIGURATIONREGISTER.
InternalUser-ProgrammableRegisters
INSTRUCTIONRAM
TheinstructionRAMholdsuptoeightsequentiallyexecutableinstructions.Each48-bitlonginstructionisdivided
into three 16-bit sections. READ and WRITE operations can be issued to each 16-bit section using the
instruction'saddressandthe2-bit“RAMpointer” intheConfigurationregister.Theeightinstructionsarelocated
at addresses 0000through0111(A4– – A1,BW=0)whenusinga16-bitwidedatabusorataddresses00000
through01111(A4– A0,BW=1)whenusingan8-bitwidedatabus.Theycanbeaccessedandprogrammedin
randomorder.
AnyInstructionRAMREADorWRITEcanaffectthesequencer'soperation:
The Sequencer should be stopped by setting the RESET T bit to a “1” ” or by resetting the START T bit in the
Configuration Register and waiting for the current instruction to finish execution before any Instruction RAM
READ or WRITE is initiated. Bit 0 of the Configuration Register indicates the Sequencer Status. See
CONFIGURATIONREGISTERforinformationontheConfigurationRegister.
AsoftRESETshouldbeissuedbywritinga“1” totheConfigurationRegister'sRESET T bit afteranyREADor
WRITEtotheInstructionRAM.
ThethreesectionsintheInstructionRAMareselectedbytheConfigurationRegister's2-bit“RAMPointer”,bits
D8andD9.Thefirst16-bitInstructionRAMsectionisselectedwiththeRAMPointerequalto“00”.Thissection
provides multiplexerchannel selection,as well as resolution, acquisition time, etc. Thesecond 16-bit section
holds“watchdog” limit#1,itssign,andanindicatorthatshows thataninterruptcanbegeneratedif theinput
signalisgreaterorlessthantheprogrammedlimit.Thethird16-bitsectionholds“watchdog” limit#2,itssign,
andanindicatorthat showsthat an interruptcanbe generated iftheinput signal isgreater orlessthanthe
programmedlimit.
InstructionRAM“ 00”
Bit0istheLOOPbit.Itindicatesthelastinstructiontobeexecutedinanyinstructionsequencewhenitissetto
a“1”.Thenextinstructiontobeexecutedwillbeinstruction0.
Bit1isthePAUSEbit.ThiscontrolstheSequencer'soperation.WhenthePAUSEbitisset(“1”),theSequencer
will stop after reading the current instruction, but before executing it and the start bit, in the Configuration
register,isautomaticallyresettoa“0”.SettingthePAUSEalsocausesaninterrupttobeissued.TheSequencer
isrestartedbyplacinga“1” intheConfigurationregister'sBit0(Startbit).
After the Instruction RAM M has been programmed and the RESET T bit is set to “1”, the Sequencer retrieves
Instruction000, decodes it, andwaitsfora“1” ” tobeplacedintheConfiguration'sSTART T bit.TheSTART bit
valueof“0” “overrides” theactionofInstruction000'sPAUSEbitwhentheSequencerisstarted.Oncestarted,
theSequencerexecutesInstruction000andretrieves,decodes,andexecuteseachoftheremaininginstructions.
NoPAUSEInterrupt(INT5)isgeneratedthefirsttimetheSequencerexecutesInstruction000havingaPAUSE
bitsetto“1”.WhentheSequencerencountersaLOOPbitorcompletesalleightinstructions,Instruction000is
retrieved anddecoded. Aset PAUSE bit inInstruction 000 nowhaltstheSequencer beforetheinstructionis
executed.
Bits2– 4selectwhichoftheeightinputchannels(“000” to“111” forIN0– – IN7)willbeconfiguredasnon-inverting
inputstotheLM12L458'sADC.(SeeTable4.)
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