The most catastrophic failure condition would be a short circuit of the series regulating
device Q1, so that the higher unregulated header voltage V
is now presented to the output
terminals. Under such fault conditions, both voltage control and current limit actions are
lost, and the “crowbar” SCR must be activated to short-circuit the output terminals.
In response to an overvoltage fault, the “crowbar” circuit responds as follows: As the
voltage across the output terminals rises above the “crowbar” actuation voltage, zener
diode ZD1 conducts driving current via R4 into the SCR gate delay capacitor C1. After a
short delay period defined by the values of C1, R4 and the applied voltage, C1 will have
charged to the gate firing voltage (0.6 V), and the SCR will conduct to short-circuit the
output terminals via the low-value limiting resistor R5. However, a large current now flows
from the unregulated DC input through the shunt-connected “crowbar” SCR. To prevent
over-dissipation in the SCR, it is normal, in linear regulators, to fit a fuse FS1 or circuit
breaker in the unregulated DC supply. If the series regulator device Q1 has failed, the fuse
or circuit breaker now clears, to disconnect the prime source from the output before the
“crowbar” SCR is destroyed.
The design conditions for such a system are well defined. It is simply necessary to select
an SCR “crowbar” or other shunt device that is guaranteed to survive the fuse or circuit
breaker’s “let-through” energy. With SCRs and fuses, this “let-through” energy is normally
defined in terms of the I2t product, where I is the fault current and t the fuse or breaker
clearance time. (See Part 1, Chap. 5.)
Crowbar protection is often preferred and hence specified by the systems engineer
because it is assumed to provide full protection (even for externally caused overvoltage
conditions). However, full protection may not always be provided, and the systems engi-
neer should be aware of possible anomalous conditions.
In standard, “off-the-shelf” power supply designs, the crowbar SCR is chosen to protect
the load from internal power supply faults. In most such cases, the maximum let-through
energy under fault conditions has been defined by a suitably selected internal fuse. The
power supply and load are thus 100% protected for internal fault conditions. However,
in a complete power supply system, there may be external sources of power, which may
become connected to the terminals of the SCR-protected power supply as a result of some
system fault. Clearly, the fault current under these conditions can exceed the rating of the
“crowbar” protection device, and the device may fail (open circuit), allowing the overvolt-
age condition to be presented to the load.
Such external fault loading conditions cannot be anticipated by the power supply
designer, and it is the responsibility of the systems engineer (user) to specify the worst-case
fault condition so that suitable “crowbar” protection devices can be provided.
11.4 “CROWBAR” PERFORMANCE
More precise “crowbar” protection circuits are shown in Fig. 1.11.1b and c. The type of
circuit selected depends on the performance required. In the simple “crowbar,” there is
always a compromise choice to be made between ideal fast protection (with its tendency
toward nuisance operation) and delayed operation (with its potential for voltage overshoot
during the delay period).
For optimum protection, a fast-acting, nondelayed overvoltage “crowbar” is required.
This should have an actuation voltage level that just exceeds the normal power supply
output voltage. However, a simple fast-acting “crowbar” of this type will often give many
“nuisance” operations, since it will respond to the slightest transient on the output lines. For
example, a sudden reduction in the load on a normal linear regulator will result in some out-
put voltage overshoot. (The magnitude of the overshoot depends on the transient response
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11. OVERVOLTAGE PROTECTION
of the power supply and the size of the transient load.) With a very fast acting “crowbar,”
this common transient overvoltage condition can result in unnecessary “crowbar” operation
and shutdown of the power supply. (The current limiting circuit would normally limit the
fault current in this type of nuisance operation, so it usually would only require a power
on-off recycling to restore the output.) To minimize such nuisance shutdowns, it is normal
practice to provide a higher trip voltage and some delay time. Hence, in the simple “crow-
bar” circuit, a compromise choice must be made among operating voltage, delay time, and
Figure 1.11.1d1 shows the response of a typical delayed “crowbar” to an overvoltage
fault condition in a linear regulator. In this example, the regulator transistor Q1 has failed to
a short circuit at instant t
. In this failure mode, the output voltage is rapidly increasing from
the normal regulated terminal voltage V
toward the unregulated header voltage V
at a rate
defined by the loop inductance, the source resistance, and the size of the output capacitors
C0. The crowbar has been set to operate at 5.5 V, which occurs at instant t
; however, because
of the crowbar delay (t
) of 30 μs (typical values), there is a voltage over-shoot. In the
example shown, the rate of change of voltage on the output terminals is such that the crowbar
operates before the output voltage has reached 6 V. At this time the output voltage is clamped
to a low value V
during the clearance time of the fuse (t
), at which time the voltage falls
to zero. Hence, full protection of an external IC load would be provided.
In this example the SCR delay time was selected to be compatible with the 20-μs tran-
sient response typical of a linear regulator. Although this delay will prevent nuisance shut-
downs, it is clear that if the maximum output voltage during the delay period is not to
exceed the load rating (normally 6.25 for 5-V ICs), then the maximum dv/dt (rate of change
of output voltage under fault conditions) must be specified. The power supply designer
should examine the failure mode, because with small output capacitors and low fault source
resistance, the dv/dt requirements may not be satisfied. Fortunately the source resistance
need is often met by the inevitable resistance of the transformer, rectifier diodes, current
sense resistors, and series fuse element.
11.5 LIMITATIONS OF “SIMPLE” CROWBAR
The well-known simple crowbar circuit shown in Fig. 1.11.1a is popular for many non-
critical applications. Although this circuit has the advantages of low cost and circuit sim-
plicity, it has an ill-defined operating voltage, which can cause large operating spreads.
It is sensitive to component parameters, such as temperature coefficient and tolerance
spreads in the zener diode, and variations in the gate-cathode operating voltage of the
SCR. Furthermore, the delay time provided by C1 is also variable, depending upon the
overvoltage stress value, the parameters of the series zener diode ZD1, and the SCR gate
When an overvoltage condition occurs, the zener diode conducts via R4, to charge C1
toward the SCR gate firing voltage. The time constant of this charge action is a function of
the slope resistance of ZD1. This is defined by the device parameters and the current flow-
ing in ZD1, which is a function of the applied stress voltage. Hence, the slope resistance of
ZD1 quite variable, giving large spreads in the operating delay of the SCR. The only sav-
ing grace in this circuit is that the delay time tends to be reduced as the overvoltage stress
condition increases. Resistor R1 is fitted to ensure that the zener diode will be biased into
its linear region at voltages below the gate firing voltage to assist in the definition of the
output actuating voltage. A suitable bias point is shown on the characteristics of the zener
diode in Fig. 1.11.1e.
A much better arrangement is shown in Fig. 1.11.1b. In this circuit a precision reference
is developed by integrated circuit reference ZD2 (TL 431 in this example). This, together
with comparator amplifier IC1 and the voltage divider network R2, R3, defines the oper-
ating voltage for the SCR. In this arrangement, the operating voltage is well defined and
independent of the SCR gate voltage variations. Also, R4 can have a much larger resistance,
and the delay (time constant R4, C1) is also well defined. Because the maximum ampli-
fier output voltage increases with applied voltage, the advantage of reduced delay at high
overvoltage stress conditions is retained. This second technique is therefore recommended
for more critical applications.
Several dedicated overvoltage control ICs are also available; a typical example is shown
in Fig. 1.11.1c. Take care to choose an IC specifically designed for this requirement, as
some voltage control ICs will not operate correctly during the power-up transient (just
when they may be most needed).
11.6 TYPE 2, OVERVOLTAGE CLAMPING
In low-power applications, overvoltage protection may be provided by a simple clamp
action. In many cases a shunt-connected zener diode is sufficient to provide the required
overvoltage protection. (See Fig. 1.11.2a.) If a higher current capability is required, a
more powerful transistor shunt regulator may be used. Figure 1.11.2b shows a typical
FIG. 1.11.2 Shunt regulator-type voltage clamp circuits.
It should be remembered that when a voltage clamping device is employed, it is
highly dissipative, and the source resistance must limit the current to acceptable levels.
Hence, shunt clamping action can be used only where the source resistance (under
failure conditions) is well defined and large. In many cases shunt protection of this
type relies on the action of a separate current or power limiting circuit for its protective
An advantage of the clamp technique is that there is no delay in the voltage clamp
action, and the circuit does not require resetting upon removal of the stress condition. Very
11. OVERVOLTAGE PROTECTION
often, overvoltage protection by clamp action is better fitted at the load end of the supply
lines. In this position it becomes part of the load system design.
11.7 OVERVOLTAGE CLAMPING WITH SCR
It is possible to combine the advantages of the fast-acting voltage clamp with the more
powerful SCR crowbar. With this combination, the delay required to prevent spurious
operation of the SCR will not compromise the protection of the load, as the clamp circuit
will provide protection during this delay period.
For lower-power applications, the simple expedient of combining a delayed crowbar as
shown in Fig. 1.11.1a with a parallel zener clamp diode (Fig. 1.11.2a) will suffice.
In more critical high-current applications, simple zener clamp techniques would be
excessively dissipative, but without voltage clamping the inevitable voltage overshoot
caused by the delay in the simple crowbar overvoltage protection circuit would be unac-
ceptable. Furthermore, nuisance shutdowns caused by fast-acting crowbars would also be
For such critical applications, a more complex protection system can be justified.
The combination of an active voltage clamp circuit and an SCR crowbar circuit with
self-adjustable delay can provide optimum performance, by eliminating nuisance shut-
downs and preventing voltage overshoot during the SCR delay period. The delay time
is arranged to reduce when the stress is large to prevent excessive dissipation during the
clamping period. (Figure 1.11.3a shows a suitable circuit, and Fig. 1.11.3b the operating
In the circuit shown in Fig. 1.11.3a, the input voltage is constantly monitored by com-
parator amplifier A1, which compares the internal reference voltage ZD1 with the input
power supply), using the divider chain R1, R2. (Voltage adjustment is pro-
vided by resistor R1.) In the event of an overvoltage stress, A1 increases and the output
of A1 goes high; current then flows in the network R4, ZD2, Q1 base-emitter, and R6. This
current turns on the clamp transistor Q1.
Q1 now acts as a shunt regulator and tries to maintain the terminal voltage at the clamp
value by shunting away sufficient current to achieve this requirement. During this clamping
action, zener diode ZD2 is polarized, and point A voltage increases by an amount defined
by the zener diode voltage, the base-emitter voltage of Q1, and a further voltage defined
by the clamp current flowing in R6. This total voltage is applied to the SCR via the series
network R7, C1, R8 such that C1 will be charging toward the gate firing voltage of the
SCR. If the overvoltage stress condition continues for a sufficient period, C1 will charge
to 0.6 V, and SCR1 will fire to short-circuit the supply to the common line. (Resistor
R9 limits the peak current in SCR1.)
The performance parameters of this circuit are shown in Fig. 1.11.3b. For a limited
stress condition, trace A will be produced as follows: At time t
an overvoltage fault
condition occurs and the voltage rises to the voltage clamp point V
. At this point, Q1
conducts to shunt away sufficient current to maintain the voltage constant at V
. At this instant, SCR1 is fired, to reduce the output voltage to a low value defined
by the SCR saturation voltage. At time t
the external fuse or circuit breaker operates to
disconnect the supply. It is clear from this diagram that if the clamping action were not
provided, the voltage could have risen to an unacceptably high value during the delay
period as a result of the long delay and the rapidly rising edge on the stress voltage
If the current flowing in Q1 during a clamping period is large, the voltage across emitter
resistor R6 will rapidly increase, increasing the voltage at point A. As a result, the delay
time for SCR1 will be reduced to t
, and the shorter delay reduces the stress and overvoltage
excursion on Q1. This is depicted by trace B in Fig. 1.11.3b.
Finally, for highly stressful conditions where the current during the clamping period
is very large, the voltage across R6 will be high enough to bring zener diode ZD3 into
FIG. 1.11.3 (a) OVP combination circuit, showing an active voltage clamp combined with an
SCR crowbar. (b) Operating characteristics for the OVP combination circuit shown in (a).
11. OVERVOLTAGE PROTECTION
conduction, bypassing the normal delay network. SCR1 will operate almost immediately
, shutting down the supply. This is shown by trace C in the diagram.
This circuit provides the ultimate in overvoltage protection, minimizing nuisance shut-
downs by providing maximum delay for small, low-stress overvoltage transient conditions.
The delay time is progressively reduced as the overvoltage stress becomes larger, and for
a genuine failure, very little delay and overshoot is allowed. This technique should be
considered as part of an overall system strategy, and the components selected to satisfy the
maximum stress conditions.
11.8 SELECTING FUSES FOR SCR “CROWBAR”
OVERVOLTAGE PROTECTION CIRCUITS
In the event of an overvoltage stress condition caused by the failure of the series regulator
in a linear power supply, the “crowbar” SCR will be required to conduct and clear the stress
condition by blowing the series protection fuse. Hence, the designer must be confident
that the fuse will open and clear the faulty circuit before the SCR is destroyed by the fault
If a large amount of energy is absorbed in the junction of the SCR within a short period,
the resultant heat cannot be conducted away fast enough. As a result, an excessive tem-
perature rise occurs, and thermal failure soon follows. Hence, the failure mechanism is
not simply one of total energy but is linked to the time period during which the energy is
For periods below 10 ms, very little of the energy absorbed at the junction interface
will be conducted away to the surrounding package or heat sink. Consequently, for a very
short transient stress, the maximum energy limit depends on the mass of the junction; this
is nearly constant for a particular device. For SCRs, this energy limit is normally specified
as a 10-ms I2t rating. For longer-duration lower-stress conditions, some of the heat energy
will be conducted away from the junction, increasing the I2t rating.
In the SCR, the energy absorbed in the junction is more correctly (I2R
is the junction slope resistance and V
is the diode voltage drop. However, at high
losses predominate, and since the slope resistance R
tends to be a constant
for a particular device, the failure energy tends to KI2t.
The same general rules as were considered for the SCR failure mechanism apply to
the fuse clearance mechanism. For very short time periods (less than 10 ms), very little of
the energy absorbed within the fuse element will be conducted away to the case, the fuse
clips, or the surrounding medium (air, sand, etc.). Once again, the fusing energy tends to be
constant for short periods, and this is defined in terms of the 10-ms I2t rating for the fuse.
For longer-duration lower-stress conditions, some of the heat energy will be conducted
away, increasing the I2t rating. Figure 1.5.1 shows how the I2t rating of a typical fast fuse
changes with stress duration.
Modern fuse technology is very sophisticated. The performance of the fuse can be modi-
fied considerably by its design. Fuses with the same long-term fusing current can behave
entirely differently for short transient conditions. For motor starting and other high-inrush
loading requirements, “slow-blow” fuses are chosen. These fuses are designed with rela-
tively large thermal mass fuse elements that can absorb considerable energy in the short
term without fuse rupture. Hence they have very high I2t ratings compared with their lon-
ger-term current ratings.
At the other end of the scale, fast semiconductor fuses have very low fuse element mass.
These fuses are often filled with sand or alumina so that the heat generated by normal
loading currents can be conducted away from the low-mass fuse element, giving higher
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