Data Distribution Systems
In many industrial and process control applications, multiple programmable voltage
sources are required. Traditionally, these applications have required a large number of
components, but recent product developments have greatly reduced the parts count
without compromising performance.
Multiple voltage outputs can either be derived by demultiplexing the output of a single
DAC or by employing multiple DACs. These two approaches are shown in Figure 8.46.
In the demultiplexed circuit (A), one DAC feeds the inputs of several sample-and-hold
amplifiers (SHA). The equivalent digital value for the analog output is applied to the
DAC, and the appropriate SHA is selected. After the DAC settling time and SHA
acquisition time requirements have been met, the SHA can be deselected and the next
channel updated. Once a SHA is deselected, the output voltage will begin to droop at a
rate specified for the SHA. Thus, the SHA must be refreshed before the output voltage
droop exceeds the required accuracy (typically ½ LSB).
Figure 8.46: Options for Analog Data Distribution
The DAC plus SHA system evolved because, in the past, DACs were more expensive
than SHAs. This situation was particularly true for DACs with resolution above 8 bits. In
addition, multiple-SHAs with on-chip hold capacitors reduced the parts count, printed
circuit board area, and cost of demultiplexed DAC systems. Finally, the demultiplexed
DAC only required one calibration step, since the same DAC provides the output voltage
for each of the output channels. Of course, single-calibration is only valid if the SHA
does not introduce unacceptable errors.
Today, however, the DAC plus SHA approach is virtually obsolete because of the
availability of high resolution, low cost integrated circuit DACs in duals, quads, octals,
etc. The multiple DAC application shown in Figure 8.46B is straightforward. One DAC
(A) DEMULTIPLEXED SINGLE DAC
(B) MULTIPLE DACS
is provided for each channel, and an address decoder simply selects the appropriate DAC.
No refresh is required.
There is a high demand not only for multiple DACs in a single package, but also for
single DACs in small low cost low power packages. Figure 8.47 shows two methods for
distributing data to several remote locations. The method shown in Figure 8.47A uses
multiple DACs to distribute analog data to multiple remote locations. This method
requires that the analog signals be protected from noise pickup, and requires the use of
shielded cables. If the remote stages are located a long distance from the source, then the
method of Figure 8.47B is preferred, where the digital data is transmitted over the remote
cable link, and individual DACs are used as each of the remote stages.
Figure 8.47: Remote, Multichannel Data Distribution
An excellent example of a low cost single DAC is the AD5320 12-bit buffered voltage
output DAC (Reference 5). A simplified block diagram is shown in Figure 8.48. AD5320
is one of a family of pin-compatible DACs. The AD5300 is the 8-bit version and the
AD5310 is the 10-bit version. The AD5300/AD5310/AD5320 are available in 6-lead
SOT-23 packages and 8-lead µSOIC packages.
The AD5320 operates from a single +2.7-V to +5.5-V supply consuming 115 µA at 3 V.
Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The
AD5320 utilizes a versatile three-wire serial interface that operates at clock rates up to
30 MHz and is compatible with standard SPI
interface standards. The reference for AD5320 is derived from the power supply inputs
and thus gives the widest dynamic output range.
ANALOG SIGNAL DISTRIBUTION
DIGITAL SIGNAL DISTRIBUTION
Figure 8.48: AD5320 12-Bit Serial Input DAC in SOT-23 6-Pin Package
The part incorporates a power-on reset circuit that ensures that the DAC output powers
up to zero volts and remains there until a valid write takes place to the device. The part
contains a power-down feature that reduces the current consumption of the device to
200 nA at 5 V and provides software selectable output loads while in power-down mode.
The part is put into power-down mode over the serial interface. The low power
consumption of this part in normal operation makes it ideally suited to portable battery
operated equipment. The power consumption is 0.7 mW at 5 V reducing to 1 µW in
There are many other single DACs in small packages with and without on-chip
references. Resolutions range from 8- to 16-bits. Selection guides are helpful in selecting
the right one for a particular application. One of the newer parts is the AD5660 16-Bit
serial input DAC with a 10-ppm/°C on-chip voltage reference (Reference 6). This device
is available in an 8-lead SOT-23 package and operates on a supply voltage of +2.7 V to
For operation at higher supply voltages, the AD5570 (Reference 7) is a single 16-bit
serial input, voltage output DAC that operates from supply voltages of ±12 V up to
±15 V. INL and DNL are accurate to 1-LSB (max) over the full temperature range of
–40°C to +125°C. The AD5570 utilizes a versatile three-wire interface. The AD5570 is
available in a 16-pin SSOP package.
For localized distribution of multiple analog signals, dual, quad, octal, etc., DACs are
generally much preferred to single DACs. Multiple DACs find applications in
instrumentation, process control, ATE, and many other applications. These DACs are
generally double-buffered so that data can be loaded via a serial port and then the actual
internal parallel DAC register updated either simultaneously or individually. Again, these
DACs are available in many resolutions, voltage/current ranges, supply voltage,
packages, etc., so a complete discussion of all options is impossible here. We will look at
a couple of newer offerings as examples.
The AD5516 consists of sixteen 12-bit DACs in a single package (Reference 8). A
functional block diagram is shown in Figure 8.49. A single reference input pin (REF_IN)
is used to provide a 3 V reference for all 16 DACs. To update a DAC's output voltage,
the required DAC is addressed via the 3-wire serial interface. Once the serial write is
complete, the selected DAC converts the code into an output voltage. The output
amplifiers translate the DAC output range to give the appropriate voltage range (±2.5 V,
±5 V, or ±10 V) at output pins V
0 to V
15. The AD5516 uses a self-calibrating
architecture to achieve 12-bit performance. The calibration routine servos to select the
appropriate voltage level on an internal 14-bit resolution. The AD5516 is available a 74-
lead CSPBGA package with a body size of 12 mm × 12 mm.
Figure 8.49: AD5516 16-Channel 12-Bit Voltage Output DAC
For the maximum available channel count today, the AD5379 contains forty 14-bit DACs
in 13mm × 13 mm 108-lead LFBGA package and is ideal for high-end level setting needs
in automatic test equipment and in optical networking applications (Reference 9). It has
both parallel and 3-wire serial interfaces. A simplified block diagram is shown in Figure
The AD5379 has a maximum output voltage span of 17.5 V which corresponds to an
output range of –8.75 V to +8.75 V derived from reference voltages of –3.5 V and +5 V.
The AD5379 contains a double-buffered parallel interface in which 14 data bits are
loaded into one of the input registers under the control of the
CS and DAC channel
address pins, A0–A7. It also has a 3-wire serial interface which is compatible with SPI
and DSP interface standards and can handle clock speeds of up
to 50 MHz. The DAC outputs are updated on reception of new data into the DAC
registers. All the outputs can be updated simultaneously by taking the
LDAC input low.
Each channel has a programmable gain and offset adjust register. Each DAC output is
gained and buffered on-chip with respect to an external REFGND input. The DAC
outputs can also be switched to REFGND via the
Figure 8.50: AD5379 40-Channel, 14-Bit, Parallel and Serial Input,
Data Distribution Using an Infinite Sample-and-Hold
An "infinite," or "droopless" sample-and-hold function can be obtained using an ADC
and a DAC. For example, the AD5533B 32-channel "infinite sample-and-hold" can be
thought of as consisting of an ADC and 32 DACs in a single package (Reference 10). A
functional diagram is shown in Figure 8.51. The input voltage V
is sampled and
converted into a digital word. The digital result is loaded into one of the DAC registers
and is converted (with gain and offset) into an analog output voltage (V
Since the channel output voltage is effectively the output of a DAC, there is no droop
associated with it. As long as power to the device is maintained, the output voltage will
remain constant until this channel is addressed again.
To update a single channel's output voltage, the required new voltage level is set up on
the common input pin, V
. The desired channel is then addressed via the parallel port or
the serial port. When the channel address has been loaded, provided
TRACK is high, the
circuit begins to acquire the correct code to load to the DAC so that the DAC output
matches the voltage on V
BUSY pin goes low and remains so until the acquisition
is complete. The noninverting input to the output buffer is tied to V
acquisition period to avoid spurious outputs while the DAC acquires the correct code.
The acquisition is completed in 16-µs max.
Figure 8.51: AD5533B 32-Channel Precision Infinite Sample-and-Hold
BUSY pin goes high and the updated DAC output assumes control of the output
voltage. The output voltage of the DAC is connected to the noninverting input of the
output buffer. Since the internal DACs are offset by 70-mV (max) from GND, the
in infinite SHA mode is 70 mV. The maximum V
is 2.96 V, due to the
upper dead band of 40-mV (max). On power-on, all the DACs, including the offset
channel, are loaded with zeros. Each of the 32 DACs is offset internally by 50-mV (typ)
from GND so the outputs V
0 to V
31 are 50-mV (typ) on power-on if the OFFS_IN
pin is driven directly by the on-board offset channel (OFFS_OUT), i.e., if OFFS_IN =
OFFS_OUT = 50 mV = > V
= (Gain × V
) – (Gain – 1) × V
= 50 mV.
The output voltage range is determined by the offset voltage at the OFFS_IN pin and the
gain of the output amplifier. It is restricted to a range from V
+ 2 V to V
– 2 V
because of the headroom of the output amplifier.
The AD5533B is operated with AV
= +5 V ± 5%, DV
= +2.7 V to +5.25 V,
= –4.75 V to –16.5 V, and V
= +8 V to +16.5 V, and requires a stable 3-V
reference on REF_IN as well as an offset voltage on OFFS_IN.
The AD5533B infinite sample-and-hold is ideally suited for use in automatic test
equipment. Several ISHAs are required to control pin drivers, comparators, active loads,
and signal timing as shown in Figure 8.52. Traditionally, sample-and-hold devices with
droop were used in these applications. These required refreshing to prevent the voltage
from drifting. The AD5533B has several advantages: no refreshing is required, there is no
droop, pedestal error is eliminated, and there is no need for extra filtering to remove
glitches. Overall, a higher level of integration is achieved in a smaller area.
Figure 8.52: Infinite Sample-and-Holds (ISHAs)
Used in Automatic Test Equipment Systems
The AD5533B can be used to set up voltage levels on 32 channels as shown in Figure
8.53. An AD780 provides the 3-V reference for the AD5533B, and for the AD5541
16-bit DAC. A simple 3-wire serial interface is used to write to the AD5541. Because the
AD5541 has an output resistance of 6.25 kΩ (typ), the time taken to charge/ discharge the
capacitance at the V
pin is significant. Thus an AD820 is therefore used to buffer the
DAC output. Note that it is important to minimize noise on V
and REFIN when laying
out this circuit.
Figure 8.53: AD5533B Infinite Sample-and-Hold Typical Application Circuit
8.2 MULTICHANNEL DATA ACQUISITION SYSTEMS
1. Data sheet for AD7908/AD7918/AD7928 8-Channel, 1 MSPS 8-/10-/12-Bit ADCs with Sequencer in
20-Lead TSSOP, http://www.analog.com.
2. Data sheet for AD7938/AD7939 8-Channel, 1.5MSPS, 12- and 10-Bit Parallel Output ADCs with a
3. Data sheet for AD7739 8-Channel, High Throughput, 24-Bit Σ-∆ ADC, http://www.analog.com.
4. Data sheet for AD7865 AD7865 4-Channel Simultaneous Sampling 14-Bit SAR ADC,
5. Data sheet for AD5320 +2.7 V to +5.5 V, 140 µA, Rail-to-Rail Output 12-Bit DAC in a SOT-23,
6. Data sheet for AD5660 16-Bit DAC with 10ppm/°C Max On-Chip Reference, http://www.analog.com.
7. Data sheet for AD5570 12-V/15-V, Serial Input, Voltage Output, 16-Bit DAC,
8. Data sheet for AD5516 16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode,
9. Data sheet for AD5379 40-Channel, 14-Bit, Parallel and Serial Input, Voltage-Output DAC,
10. Data sheet for AD5533B 32-Channel Precision Infinite Sample-and-Hold, http://www.analog.com.
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