display pdf winform c# : Rotate all pages in pdf and save Library SDK class asp.net wpf winforms ajax 74HC_HCT5950-part732

1. General description
The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a 
storage register and 3-state outputs. Both the shift and storage register have separate 
clocks. The device features a serial input (DS) and a serial output (Q7S) to enable 
cascading and an asynchronous reset MR
input. A LOW on MR
will reset the shift register. 
Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift 
register is transferred to the storage register on a LOW-to-HIGH transition of the STCP 
input. If both clocks are connected together, the shift register will always be one clock 
pulse ahead of the storage register. Data in the storage register appears at the output 
whenever the output enable input (OE
) is LOW. A HIGH on OE
causes the outputs to 
assume a high-impedance OFF-state. Operation of the OE
input does not affect the state 
of the registers. Inputs include clamp diodes. This enables the use of current limiting 
resistors to interface inputs to voltages in excess of V
CC
2.  Features and benefits
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100MHz (typical) shift out frequency
Complies with JEDEC standard no. 7A
Input levels:
For 74HC595: CMOS level
For 74HCT595: TTL level
ESD protection:
HBMJESD22-A114F exceeds2000V
MMJESD22-A115-A exceeds200V
Multiple package options
Specified from 
40
C to+85
C and from 
40
C to+125
C
3.  Applications
Serial-to-parallel data conversion
Remote control holding register
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output 
latches; 3-state
Rev. 8 — 25 February 2016
Product data sheet
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74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 25 February 2016 
2 of 23
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
4.  Ordering information
5.  Functional diagram
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74HC595D
40
C to +125
C
SO16
plastic small outline package; 16leads; 
bodywidth3.9mm
SOT109-1
74HCT595D
74HC595DB
40
C to +125
C
SSOP16
plastic shrink small outline package; 16leads; 
bodywidth 5.3mm
SOT338-1
74HCT595DB
74HC595PW
40
C to +125
C
TSSOP16
plastic thin shrink small outline package; 16leads; 
body width 4.4mm
SOT403-1
74HCT595PW
74HC595BQ
40
C to +125
C
DHVQFN16
plastic dual in-line compatible thermal enhanced 
very thin quad flat package; no leads; 16terminals; 
body 2.5 
3.5 
0.85 mm
SOT763-1
74HCT595BQ
Fig 1. Functional diagram
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74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 25 February 2016 
3 of 23
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Fig 2. Logic symbol
Fig 3. IEC logic symbol
2(
05











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74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 25 February 2016 
4 of 23
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
6.  Pinning information
6.1 Pinning
6.2 Pin description
(1) This is not a supply pin. The substrate is attached to this 
pad using conductive die attach material. There is no 
electrical or mechanical requirement to solder this pad. 
However, if it is soldered, the solder land should remain 
floating or be connected to GND.
Fig 5. Pin configuration SO16, SSOP16 and 
TSSOP16
Fig 6. Pin configuration for DHVQFN16
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Table 2.
Pin description
Symbol
Pin
Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
15, 1, 2, 3, 4, 5, 6, 7
parallel data output
GND
8
ground (0 V)
Q7S
9
serial data output
MR
10
master reset (active LOW)
SHCP
11
shift register clock input
STCP
12
storage register clock input
OE
13
output enable input (active LOW)
DS
14
serial data input
Q0
15
parallel data output 0
V
CC
16
supply voltage
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74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 25 February 2016 
5 of 23
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
7.  Functional description
[1] H=HIGH voltage state;
L=LOW voltage state;
=LOW-to-HIGH transition;
X=don’t care;
NC=no change;
Z=high-impedance OFF-state.
Table 3.
Function table
[1]
Control
Input
Output
Function
SHCP
STCP
OE
MR
DS
Q7S
Qn
X
X
L
L
X
L
NC
a LOW-level on MR
only affects the shift registers
X
L
L
X
L
L
empty shift register loaded into storage register
X
X
H
L
X
L
Z
shift register clear; parallel outputs in high-impedance OFF-state
X
L
H
H
Q6S
NC
logic HIGH-level shifted into shift register stage 0. Contents of all 
shift register stages shifted through, e.g. previous state of stage 6 
(internal Q6S) appears on the serial output (Q7S).
X
L
H
X
NC
QnS
contents of shift register stages (internal QnS) are transferred to 
the storage register and parallel output stages
L
H
X
Q6S
QnS
contents of shift register shifted through; previous contents of the 
shift register is transferred to the storage register and the parallel 
output stages
Fig 7. Timing diagram
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74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 25 February 2016 
6 of 23
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
8.  Limiting values
[1] For SO16 package: P
tot
derates linearly with 8mW/K above 70 
C.
[2] For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5mW/K above 60 
C.
[3] For DHVQFN16 package: P
tot
derates linearly with 4.5mW/K above 60 
C.
9.  Recommended operating conditions
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
V
CC
supply voltage
0.5
+7
V
I
IK
input clamping current
V
I
0.5V or V
I
>V
CC
+0.5 V
-
20
mA
I
OK
output clamping current
V
O
<
0.5V or V
O
> V
CC
+ 0.5 V
-
20
mA
I
O
output current
V
O
=
0.5V to (V
CC
+0.5V)
pin Q7S
-
25
mA
pins Qn
-
35
mA
I
CC
supply current
-
70
mA
I
GND
ground current
70
-
mA
T
stg
storage temperature
65
+150
C
P
tot
total power dissipation
SO16 package
[1]
-
500
mW
SSOP16 package
[2]
-
500
mW
TSSOP16 package
[2]
-
500
mW
DHVQFN16 package
[3]
-
500
mW
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
74HC595
74HCT595
Unit
Min
Typ
Max
Min
Typ
Max
V
CC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
V
I
input voltage
0
-
V
CC
0
-
V
CC
V
V
O
output voltage
0
-
V
CC
0
-
V
CC
V
t/
V
input transition rise and 
fall rate
V
CC
=2.0V
-
-
625
-
-
-
ns/V
V
CC
=4.5V
-
1.67
139
-
1.67
139
ns/V
V
CC
=6.0V
-
-
83
-
-
-
ns/V
T
amb
ambient temperature
40
+25
+125
40
+25
+125
C
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 25 February 2016 
7 of 23
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Symbol
Parameter
Conditions
40
C to +85
C
40
C to +125
C
Unit
Min
Typ
Max
Min
Max
74HC595
V
IH
HIGH-level 
inputvoltage
V
CC
=2.0V
1.5
1.2
-
1.5
-
V
V
CC
=4.5V
3.15
2.4
-
3.15
-
V
V
CC
=6.0V
4.2
3.2
-
4.2
-
V
V
IL
LOW-level 
inputvoltage
V
CC
=2.0V
-
0.8
0.5
-
0.5
V
V
CC
=4.5V
-
2.1
1.35
-
1.35
V
V
CC
=6.0V
-
2.8
1.8
-
1.8
V
V
OH
HIGH-level 
outputvoltage
V
I
=V
IH
orV
IL
all outputs
I
O
=
20
A; V
CC
=2.0V
1.9
2.0
-
1.9
-
V
I
O
=
20
A; V
CC
=4.5V
4.4
4.5
-
4.4
-
V
I
O
=
20
A; V
CC
=6.0V
5.9
6.0
-
5.9
-
V
Q7S output
I
O
=
4mA; V
CC
=4.5V
3.84
4.32
-
3.7
-
V
I
O
=
5.2mA; V
CC
=6.0V
5.34
5.81
-
5.2
-
V
Qn bus driver outputs
I
O
=
6mA; V
CC
=4.5V
3.84
4.32
-
3.7
-
V
I
O
=
7.8mA; V
CC
=6.0V
5.34
5.81
-
5.2
-
V
V
OL
LOW-level 
outputvoltage
V
I
=V
IH
orV
IL
all outputs
I
O
=20
A; V
CC
=2.0V
-
0
0.1
-
0.1
V
I
O
=20
A; V
CC
=4.5V
-
0
0.1
-
0.1
V
I
O
=20
A; V
CC
=6.0V
-
0
0.1
-
0.1
V
Q7S output
I
O
=4mA; V
CC
=4.5V
-
0.15
0.33
-
0.4
V
I
O
=5.2mA; V
CC
=6.0V
-
0.16
0.33
-
0.4
V
Qn bus driver outputs
I
O
=6mA; V
CC
=4.5V
-
0.15
0.33
-
0.4
V
I
O
=7.8mA; V
CC
=6.0V
-
0.16
0.33
-
0.4
V
I
I
input leakage 
current
V
I
=V
CC
orGND; V
CC
=6.0V
-
-
1.0
-
1.0
A
I
OZ
OFF-state 
output current
V
I
=V
IH
orV
IL
; V
CC
=6.0V; 
V
O
=V
CC
orGND
-
-
5.0
-
10
A
I
CC
supply current
V
I
=V
CC
orGND; I
O
=0A; 
V
CC
=6.0V
-
-
80
-
160
A
C
I
input 
capacitance
-
3.5
-
-
-
pF
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 25 February 2016 
8 of 23
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HCT595
V
IH
HIGH-level 
inputvoltage
V
CC
=4.5V to 5.5V
2.0
1.6
-
2.0
-
V
V
IL
LOW-level 
inputvoltage
V
CC
=4.5V to 5.5V
-
1.2
0.8
-
0.8
V
V
OH
HIGH-level 
outputvoltage
V
I
=V
IH
orV
IL
; V
CC
=4.5V
all outputs
I
O
=
20
A
4.4
4.5
-
4.4
-
V
Q7S output
I
O
=
4mA
3.84
4.32
-
3.7
-
V
Qn bus driver outputs
I
O
=
6mA
3.7
4.32
-
3.7
-
V
V
OL
LOW-level 
outputvoltage
V
I
=V
IH
orV
IL
; V
CC
=4.5V
all outputs
I
O
=20
A
-
0
0.1
-
0.1
V
Q7S output
I
O
=4.0mA
-
0.15
0.33
-
0.4
V
Qn bus driver outputs
I
O
=6.0mA
-
0.16
0.33
-
0.4
V
I
I
input leakage 
current
V
I
=V
CC
orGND; V
CC
=5.5V
-
-
1.0
-
1.0
A
I
OZ
OFF-state 
output current
V
I
=V
IH
orV
IL
; V
CC
=5.5 V; 
V
O
=V
CC
orGND
-
-
5.0
-
10
A
I
CC
supply current
V
I
=V
CC
orGND; I
O
=0A; 
V
CC
=5.5V
-
-
80
-
160
A
I
CC
additional 
supply current
per input pin; I
O
=0A; V
I
=V
CC
2.1V; otherinputsat V
CC
orGND; 
V
CC
=4.5Vto5.5V
pins MR
, SHCP, STCP, OE
-
150
675
-
735
A
pin DS
-
25
113
-
123
A
C
I
input 
capacitance
-
3.5
-
-
-
pF
Table 6.
Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Symbol
Parameter
Conditions
40
C to +85
C
40
C to +125
C
Unit
Min
Typ
Max
Min
Max
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 25 February 2016 
9 of 23
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure13
.
Symbol
Parameter
Conditions
25 
C
40
C to+85 
C
40
C to+125 
C
Unit
Min
Typ
[1]
Max
Min
Max
Min
Max
74HC595
t
pd
propagation 
delay
SHCPtoQ7S; see Figure8
[2]
V
CC
= 2 V
-
52
160
-
200
-
240
ns
V
CC
= 4.5 V
-
19
32
-
40
-
48
ns
V
CC
= 6 V
-
15
27
-
34
-
41
ns
STCPtoQn; see Figure9
[2]
V
CC
= 2 V
-
55
175
-
220
-
265
ns
V
CC
= 4.5 V
-
20
35
-
44
-
53
ns
V
CC
= 6 V
-
16
30
-
37
-
45
ns
MR
toQ7S; see Figure11
[3]
V
CC
= 2 V
-
47
175
-
220
-
265
ns
V
CC
= 4.5 V
-
17
35
-
44
-
53
ns
V
CC
= 6 V
-
14
30
-
37
-
45
ns
t
en
enable time OE
to Qn; see Figure12
[4]
V
CC
= 2 V
-
47
150
-
190
-
225
ns
V
CC
= 4.5 V
-
17
30
-
38
-
45
ns
V
CC
= 6 V
-
14
26
-
33
-
38
ns
t
dis
disable time OE
to Qn; see Figure12
[5]
V
CC
= 2 V
-
41
150
-
190
-
225
ns
V
CC
= 4.5 V
-
15
30
-
38
-
45
ns
V
CC
= 6 V
-
12
27
-
33
-
38
ns
t
W
pulse width SHCP HIGH or LOW; 
seeFigure8
V
CC
= 2 V
75
17
-
95
-
110
-
ns
V
CC
= 4.5 V
15
6
-
19
-
22
-
ns
V
CC
= 6 V
13
5
-
16
-
19
-
ns
STCP HIGH or LOW; 
seeFigure9
V
CC
= 2 V
75
11
-
95
-
110
-
ns
V
CC
= 4.5 V
15
4
-
19
-
22
-
ns
V
CC
= 6 V
13
3
-
16
-
19
-
ns
MR
LOW; seeFigure11
V
CC
= 2 V
75
17
-
95
-
110
-
ns
V
CC
= 4.5 V
15
6
-
19
-
22
-
ns
V
CC
= 6 V
13
5
-
16
-
19
-
ns
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 25 February 2016 
10 of 23
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
t
su
set-up time DS to SHCP; seeFigure9
V
CC
= 2 V
50
11
-
65
-
75
-
ns
V
CC
= 4.5 V
10
4
-
13
-
15
-
ns
V
CC
= 6 V
9
3
-
11
-
13
-
ns
SHCP to STCP; 
seeFigure10
V
CC
= 2 V
75
22
-
95
-
110
-
ns
V
CC
= 4.5 V
15
8
-
19
-
22
-
ns
V
CC
= 6 V
13
7
-
16
-
19
-
ns
t
h
hold time
DS to SHCP; seeFigure10
V
CC
= 2 V
3
6
-
3
-
3
-
ns
V
CC
= 4.5 V
3
2
-
3
-
3
-
ns
V
CC
= 6 V
3
2
-
3
-
3
-
ns
t
rec
recovery 
time
MR
to SHCP; see Figure11
V
CC
= 2 V
50
19
-
65
-
75
-
ns
V
CC
= 4.5 V
10
7
-
13
-
15
-
ns
V
CC
= 6 V
9
6
-
11
-
13
-
ns
f
max
maximum 
frequency
SHCP or STCP; 
seeFigure8
and 9
V
CC
= 2 V
9
30
-
4.8
-
4
-
MHz
V
CC
= 4.5 V
30
91
-
24
-
20
-
MHz
V
CC
= 6 V
35
108
-
28
-
24
-
MHz
C
PD
power 
dissipation 
capacitance
f
i
= 1 MHz; V
I
=GNDtoV
CC
[6]
[7]
-
115
-
-
-
-
-
pF
Table 7.
Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure13
.
Symbol
Parameter
Conditions
25 
C
40
C to+85 
C
40
C to+125 
C
Unit
Min
Typ
[1]
Max
Min
Max
Min
Max
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