THEORY OF OPERATION OF
held resolver-format signals (at points A and B in
Figure 3.4) are already DC signals proportional to
sinθ and cosθ. Unfortunately, these signals are also
proportional to the reference excitation, which can,
and does, vary over as wide a range as ±10% in
Furthermore, the rotor-to-stator transfer coefficient in
the synchro or resolver itself varies from unit to unit.
In another possible "short-cut" approach, the
resolver-format signals may be demodulated in
phase-sensitive detectors to produce DC sine/cosine
outputs; but this configuration, while essentially free
of speed-voltage is still entirely vulnerable to varia-
tions in reference excitation.
The circuit of Figure 3.4 produces nonvariant
sine/cosine outputs - i.e., outputs in which the scale
factor, K, is held constant within very narrow limits,
and is essentially independent of the reference exci-
Once again, it would be well to review pages 29 to
30, and Figure 2.11, to recall how the sampling har-
monic oscillator synchro-to-digital converter works.
The circuit of Figure 3.4 differs from that of Figure
2.11 in three important ways:
The digital counter is an up-down counter.
The output is not a digital word derived from the
counter state (at the end of the time interval t), but
is derived by sampling the levels at points A and B
in the circuit, and holding them for one carrier
cycle until the next (updated) measurement is
Additional programming logic is provided to imple-
ment the up-down count behavior described below.
The first phase of the conversion process is identical
to that described on pages 29 to 30, with the results
indicated in Figure 2.12. This phase involves:
strobed sampling and holding of the resolver-format
sine/cosine signals; setting the integrators to zero;
applying the sampled data as initial conditions to the
integrators; unclamping the loop; and allowing it (and
the clock-pulse counter) to run until the positive zero-
crossing is reached. At the end of this phase, note
that point A is at zero (which is the condition that
stopped the counter), and point B is at maximum
(cosine of zero degrees=one). Note that the actual
magnitude of the voltage at B is proportional to the
reference excitation that generated the samples
used to set the initial conditions.
The second phase of the conversion, begins by set-
ting point B to a new level that is independent of the
rotor excitation, or any other source of scale factor
uncertainty. This new level is an accurately calibrat-
ed and stabilized voltage that will establish the
desired scale factor, K, in the final output. Now hav-
ing established this new set of initial conditions, the
loop is unclamped, and allowed to run for exactly the
same time interval as it ran in first phase ... a time
interval generated by allowing the counter to count
down, at the same clock-pulse rate, to zero. At this
point, the loop is again clamped, and points A and B
are sampled and held,
to yield outputs that are
scaled correctly, and are proportional to the sine and
θ... non-variant sine/cosine outputs.
Here again, as before, the clock-pulse generator
must be phase-locked to compensate for integrator-
RC drift, and there is a maximum staleness error of
one carrier cycle.
These then are a few of the techniques used to con-
vert synchro data to nonvariant DC sine/cosine data.
There is, of course, the method gaining in popularity,
of using a microprocessor, a sine/cosine ROM and
two D/A converters to achieve the same result.
Where the microprocessor is not fully utilized this is
a good approach but for designers not wishing to fur-
ther burden it the S/D and DC-coupled D/R method
Refer to Figure 11.26 for an illustration of a syn-
chro/resolver-to-DC converter using a DDC model
RDC-19220 series converter and the Burr Brown
DAC 703 digital-to-analog converter.