The sample-and-hold of the LTC1288 allows conversion
of rapidly varying signals. The input voltage is sampled
during the t
time as shown in Figure 7. The sampling
interval begins as the bit preceding the MSBF bit is shifted
in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt-
age on the selected “–” input must remain constant and be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per-
formed accurately. The conversion time is 12 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
Where f(“–”) is the frequency of the “–” input voltage,
is its peak amplitude and f
is the frequency of the
CLK. In most cases V
will not be significant. For a
60Hz signal on the “–” input to generate a 1/4LSB error
V) with the converter running at CLK = 120kHz, its
peak value would have to be 4.03mV.
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1285/
LTC1288 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used or
if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
“+” Input Settling
The input capacitor of the LTC1285 is switched onto “+”
input during the t
time (see Figure 1) and samples
the input signal within that time. However, the input
capacitor of the LTC1288 is switched onto “+” input
during the sample phase (t
, see Figure 7). The
sample phase is 1 1/2 CLK cycles before conversion
starts. The voltage on the “+” input must settle com-
pletely within t
for the LTC1285 and the LTC1288
respectively. Minimizing R
and C1 will improve
the input settling time. If a large “+” input source resis-
tance must be used, the sample time can be increased by
using a slower CLK frequency.
“–” Input Settling
At the end of the t
, the input capacitor switches to the
“–” input and conversion starts (see Figures 1 and 7).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage settles completely during the first CLK cycle of the
conversion time and be free of noise. Minimizing R
and C2 will improve settling time. If a large “–” input
source resistance must be used, the time allowed for
settling can be extended by using a slower CLK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the“+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps, including the LT1006 and
LT1413 single supply op amps, can be made to settle well
even with the minimum settling windows of 12.5
input) which occur at the maximum clock rate of 120kHz.
The analog inputs of the LTC1285/LTC1288 look like a
20pF capacitor (C
) in series with a 500
as shown in Figure 8. C
gets switched between the