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Chap
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:
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C
ommands
s
t
ep
C
ommand
Afteryourunaninitialsimulation,youcanstepthroughyourHDLdesignonelineofsourcecodeatatimeto
verifythatthedesignisworkingasexpected.The
step
commandadvancestothenextlineofexecutablecodein
theVerilogorVHDLfile. TheequivalentGUIcommandisSimulation>Step.
No
t
e
Thiscommandiscasesensitive.
step
wherenooptionsareavailable.
Examp
l
e
TostepthroughonelineofHDLsourcecode:
step
t
es
tC
ommand
The
test
commandcomparestheactualvalueofaVHDLsignal,Verilogwire,Verilogreg,VHDLgeneric,
VerilogparameterorVHDLprocessvariableinthecurrentscopewithasuppliedvalue.Ifthetwovaluesmatch,
nothingisdisplayed. Otherwisethecurrentcorrectvalueisdisplayed,andISimreportsanerror.Youcantest
onebit,asliceofavectorelementorawholevalue.
No
t
e
Thiscommandiscasesensitive.
test
<
signal_name|vhdl_process_name/process_variable_name
>
{element reference,
element reference, ...}
<
value
>
|
<
object
> <
value
-
radix
<
radix_type
>
Op
t
i
ons
<signal_name |
vhdl_process_name/process_variable_name>
{element reference, , element t reference,
...} <value>
<signal_name>referstothenameofthesignalorbusto
becompared. Thiscanalsobethenameofanarrayof
signals/buses,anarrayofrecordscontainingsignalsand
busesorarecordofarraysofbuses/signals.
<vhdl_process_name/process_variable_name>isthenameofthe
processandprocessvariabletobecompared. Tocompare
thevalueofaprocessvariable,youmustalsosupplythe
nameoftheprocessthatcontainsthevariable. Theprocess
nameandprocessvariablenamesmustbeseparatedby"/".
{elementreference}referstothedifferentwaysinwhichthe
sub-elementsofthesignalnamecanbereferencedwhen
usedwiththe
test
command.Thisprovidestheability
tofurtherrefinethesignalsbyreferencingtheindividual
sub-elementsofasignal.PleaseseeExamplesbelowfor
moreinformation.
<value>referstothesuppliedvaluetocomparewithactual
valueonnetorbus.
<object> <value>
-
radix <radix_type>
Comparesthespecifiedvaluewiththespecifiedradixto
objectvalue.
<object>specifiesthesignals,busesorobjectstotest.
<value>referstothevalueyouwishtoaddtotheobject.
Thesupportedradixtypesare
default
,
dec
,
bin
,
oct
,
hex
,
unsigned
and
ascii
. Whennoradixtypeis
specified,theglobalradixtypesetwiththeisimsetradix
commandisused,orifnoneissetthere,
default
isusedas
radix.
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Chap
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C
ommands
Examp
l
es
The
test
commandcanbeusedasfollows.
Tocompareabitvaluesof"1"toasignalcalled
count
(6)
inthemodule
u
1
thatisinstantiatedunderyour
currentscope:
test u
1/
count
(6) 1
TocomparethevalueofsignalAto"FF":
test
A FF -
radix hex
Tocomparevaluewith"clk"value:
test clk
U
Returns
1
.
Tocomparevaluewith"clk"value:
test clk
’0’
Returns
0
.
Tostopsimulationif/top/rstis0.
if {[test
/
top
/
rst
0
] } } {stop } else
...
ForthesignalResetinBlockUut,thecommand
test
R
eset
1
displaysthefollowingmessage:
test failed
C
ommand failed
:
test
R
eset
1
1
N
et
R
eset has s value
0
not
1
as expected
.
ForthebusLsbcntinUut,thecommand
test
L
sbcnt
1001
displaysthefollowingmessage:
test passed
0
Forastandardlogicvectorcalled
sigx
anddeclaredasfollows:
signal sigx
:
std_logic_vector
(0
to
5);
Tocomparebit0of
sigx
to"1":
test sigx
(0) 1
Tocompareslice1to2of
sigx
to"11":
test sigx
(1:2) 11
Tocompareallof
sigx
to"101010":
test sigx
101010
Foranarrayofstandardlogicvectorsthatisdeclaredasfollows:
signal sigarray
:
vectorarray
(0
to
5, 1
to
4, 2
to
6);
Tocompareeverybitofavectorarrayelementof
sigarray
to"1":
test sigarray
(0,1,2)1111
Tocomparethefirsttwobitsofeacharrayelementof
sigarray
to"10":
test sigarray
(0,1,2)(1:2)10
Tocomparebitsthreeofeacharrayelementof
sigarray
to"1":
test sigarray
(0,1,2)(3)1
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Chap
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ommands
Foranarrayofrecordsthatcontainsanarrayofstandardlogicvectorsandisdeclaredasfollows:
type ram_
3
d_vector is array
(0
to
10, 7
downto
0, 0
to
2)
of std_logic_vector
(1
to
4);
type rectype is record
a
:
integer
;
b
:
string
(1
to
7);
c
:
std_logic_vector
(0
to
3);
d
:
ram_
3
d_vector
;
end record
;
type recarray y is s array
(0
to
3, 4
downto
1)
of rectype
;
signal recarrsig
:
recarray
;
signal recsig
:
rectype
;
Tocomparethesecondelement(
b
)oftherecord
recsig
tothestring"abc":
test
recsig
.
b
(2:4)
abc
Tocomparethefourbitwidevectorrepresentedbythecoordinates2,3,1inthethreedimensionalarray
d
in
therecord
recsig
to"0110":
test recsig
.
d
(2,3,1) 0110
Tocomparethefirsttwobitsofthefourbitwidevectorrepresentedbythecoordinates2,3,1inthethree
dimensionalarray
d
intherecord
recsig
to"01":
test recsig
.
d
(2,3,1)(1:2) 01
Tocomparethefourbitwidevectorrepresentedbythecoordinates2,3,1inthethreedimensionalarray
d
inthe
record
recsig
representedbythecoordinates2,2inthetwodimensionalarray
recarrsig
to"0011":
test recarrsig
(2,2).
d
(2,3,1)0011
vcd
C
ommand
The
vcd
commandgeneratessimulationresultsinVCDformat. Thiscommandenablesyoutodumpspecified
instancestoaVCDfile,tonametheVCDfile,tostartandstopthedumpprocess,andotherfunctions. See
alsoWritingActivityDataoftheDesign.
No
t
e
Thiscommandiscasesensitive.
vcd
(
option
)
Op
t
i
ons
dumpfile
<
file_name>
GivesanametoVCDfile. Defaultfilenameis
dump
.
vcd
.
InvokesVerilog$dumpfiledirective.
dumpvars
-
m
<
module_name
>
[
-
l
<
level
>
]
DumpsthespecifiedvariablesandtheirvaluestotheVCD
file.
-
m
<module_name>dumpsthemoduleofthatname.
-
l
0
-Level0causesadumpofallvariablesinthespecified
moduleandinallmoduleinstancesbelowthespecified
module. Theargument0appliesonlytosubsequent
argumentswhichspecifymoduleinstances,andnoto
individualvariables.
1
-Level1dumpsallvariablewithinthemodulespecified
by-m;itdoesnotdumpvariablesinanyofthemodules
instantiatedbythemodulespecifiedby-m.
InvokesVerilog$dumpfiledirective.
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How to C#: Preview Document Content Using XDoc.Word
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Chap
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ommands
dumpoff
Temporarilysuspendsthedumpingprocess,anddumpsall
selectedvariablesasan’X’value.InvokesVerilog$dumpoff
directive.
dumpon
Resumesthedumpingprocessafterthe
dumpoff
option
hasbeeninvoked. Dumpsallselectedvaluesatthetime
dumpon
isinvoked.InvokesVerilog$dumpondirective.
dumpall
CreatesacheckpointintheVCDfilethatdumpsthecurrent
valueofallselectedvariables.InvokesVerilog$dumpall
directive.
dumplimit
<
file_size
>
LimitsthesizeoftheVCDfile. file_sizespecifiesthe
maximumsizeoftheVCDfileinbytes.Whenthesizeof
VCDfilereachesthelimit,thedumpprocessstopsanda
commentisinsertedintheVCDfileindicatingthatthe
dumplimitwasreached. InvokesVerilog$dumplimit
directive.
dumpflush
Emptiestheoperatingsystem’sVCDfilebuffertoensure
thatallthedatainthatbufferisstoredintheVCDfile.After
executing,dumpprocessresumesasbeforesonovalue
changesarelost.InvokesVerilog$dumpflushdirective.
Examp
l
es
The
vcd
commandcanbeusedasfollows.
FollowingarethecommandsyouwouldusetowritetheVCDsimulationvaluesofthemoduleUUTtoaVCD
fileafterrunningsimulationfor1000ns.
Specifywhichfiletowrite:
vcd dumpfile adder
.
vcd
Specifywhichmodulenetactivitiestowrite:
vcd dumpvars
-
m
/
UUT
Runsimulationforgiventime:
run
1000
ns
Dumptheactivitydatatothevcdfile.
vcd dumpflush
waveadd
C
ommand
The
wave add
commandaddssimulationobjectsorblockstothespecifiedwaveconfigurationintheISim
graphicaluserinterface.ThewaveconfigurationdisplaysintheWavewindow.
TheequivalentGUIcommandisAddtoWaveWindow.
No
t
e
Thiscommandiscasesensitive.
Syn
t
ax
wave add [
-
wcfg <wcfg_name>] ] <object_name> > [<object_name>] ] [
-
r]
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VB.NET PDF File Compress Library: Compress reduce PDF size in vb.
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Add necessary references: RasterEdge.Imaging.Basic.dll. Get Preview From File. You may get document preview image from an existing Excel file in C#.net.
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Chap
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:
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C
ommands
Op
t
i
ons
-
wcfg <wcfg_name>
Determinestowhichwaveconfigurationfilethesignals/objectswillbe
added.Ifawaveconfigurationfilenameisenteredthatdoesnotalready
exist,thefilewillbecreated.
No
t
e wave e add
-
wcfg
isnotsupportedwheninbatchmode,thatis,
whenlaunchingthesimulationexecutablewithoutthe
-
gui
switch.
<
object_name> [<object_name>]
Addsoneormoreobjectstothewaveconfiguration.Anobjectiseithera
simulationobject(VHDLsignal,Verilogregorwire)orblock(instancename
ofaVHDLentityorVerilogModule).
-
r
With
-
r
,theobjectsassociatedwitheachblockareaddedtothewaveform,
downtothelowestlevelofhierarchy.Without
-
r
,thefirstlevelobjectsof
theblock(s)enteredasobject_nameareadded.
Examp
l
es
The
wave add
commandcanbeusedasfollows.
ToaddthesignalsassociatedwithobjectUUTtothecurrentwaveconfiguration:
wave add
/
tb
/
UUT
Toaddalltop-levelsignals:
wave add
/
Toaddallsignalsinthedesign:
wave add
r
/
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Appendix
Reference
S
i
mu
l
a
t
i
onExecu
t
ab
l
e
C
ommands
S
i
mu
l
a
t
i
onExecu
t
ab
l
e
C
ommandOverv
i
ew
No
t
e
Thefollowinginformationisintendedforadvancedusers.
YoucanrunISimatthecommandlineinsteadofusingtheISE®softwareortheISiminterface.
Runn
i
ngS
i
mu
l
a
t
i
on
F
r
om
t
he
C
ommandL
i
ne
TosimulateaVerilogdesignfromthecommandline,see:
RunningaFunctionalSimulationFromtheCommandLineWithaVerilogDesign
RunningaTimingSimulationFromtheCommandLineWithaVerilogDesign
TosimulateaVHDLdesignfromthecommandline,see:
RunningaFunctionalSimulationFromtheCommandLineWithaVHDLDesign
RunningaTimingSimulationFromtheCommandLineWithaVHDLDesign
Execu
t
ab
l
e
C
ommandSummary
Thereareanumberofcommandsusedtoexecuteasimulationatthecommandline.
CompilationCommands
VHDLcompiler(vhpcomp)-TheVHDLcompiler,vhpcomp,parsesVHDLsourcefilesforalldesign
unitsinthosefiles.
Verilogcompiler(vlogcomp)-TheVerilogcompiler,vlogcomp,parsesVerilogsourcefilesforalldesign
unitsinthosefiles.
ElaborationCommands
HDLlinker(fuse)-TheHDLlinker,fuse,performsstaticelaborationofadesignintermsofparsednodes,
generatesobjectcodeforeachuniquemoduleinstance,andlinksthegeneratedobjectcodeswithISimsimulation
enginelibrarytocreateasimulationexecutable. Auserrunsthisgeneratedsimulationexecutabletoeffect
simulationofthedesignunderconsideration.
SimulationCommands
SimulationExecutable-TheISESimulationExecutableisgeneratedbythefusecommand.Torunthesimulation
ofadesigninISim,thegeneratedsimulationexecutableneedstobeinvoked. WhenISimisruninsidethe
ISEinterface,ISEtakescareofinvokingthegeneratedsimulationexecutable.Acommand-lineuserneedsto
explicitlyinvokethegeneratedsimulationexecutabletoeffectsimulation. Thesimulationexecutableeffects
event-drivensimulationandhasrichsupportfordrivingandprobingsimulationusingTcl.
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Append
i
x
:
Re
f
erence
P
r
o
j
ec
t
Fil
es
Aprojectfilecanbeusedtoinvokevhpcomp,vlogcompandfuse. Youcancollectallofthedesignfilesfora
particularprojectintoaprojectfile,andusethe-prjoptiontospecifytheprojectfile.Theprojectfilecancontain
VHDLorVerilogfiles.
Eachlineinaprojectfilemustbeformattedasfollows:
<language>[<library>]<filename>{[
-
d <macro>] [
-
i <include_path>]}
where,
<language>iseither
vhdl
or
verilog
.
<library>isanoptionalworkinglibraryname.
Tc
l
C
ommands
ThesimulationexecutableprovidesapowerfulTclinterfacethatcanberuninbatchmode.Tclcommandscanbe
usedtocontrolthesimulatorandviewtheresultsofsimulation.
Invokethesimulationexecutableusingthe-tclbatchoptiontolistanumberofTclcommandsinabatchfile.
I
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i
mu
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a
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i
onExecu
t
ab
l
e
I
S
i
mS
i
mu
l
a
t
i
onExecu
t
ab
l
eOverv
i
ewandSyn
t
ax
No
t
e
Thefollowinginformationisintendedforadvancedusers.
TheISimsimulationexecutablefileisauser-definedexecutablefile. Runningthefileatthecommandline
invokesanISimsimulation.Youcansettheexecutablenameusingthe
-
o
optionofthefuseExamples.Ifnot
user-defined,thedefaultexecutablenameis
x
.
exe
.
Thesyntaxforthiscommandisasfollows:
<executable_name>
.
exe
(
option
)
where<executable_name>.exeisuserdefinedoris
x
.
exe
bydefault.
No
t
e
Thiscommandiscasesensitive.
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t
i
ons
TheISimsimulationexecutablecommandoptionsareasfollows.
No
t
e
Thiscommandiscasesensitive.
-
f <cmd_file>
YoucansaveISimenginecommandoptionsinatextfilefor
futureuse.Thisoptionreadsandexecutesthesavedoptions
thatarespecifiedincmd_file.
-
gui
LaunchestheISimgraphicaluserinterface.
-
h
Displaysallcommandlineoptionsandtheirusage.
-
intstyle
ise | | xflow w | silent
Useoneofthespecifiedstylesforprintingmessages.Specify
ise
toformatmessagesfortheISEConsoleWindowor
xflow
toformatmessagesforXFLOW.Specify
silent
to
suppressallmessages.
-
log
<
file_name
>
Generatesalogfilewithnamespecifiedbyfile_name.
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Append
i
x
:
Re
f
erence
-
maxdeltaid
<
number
>
Specifiesthemaximumdeltanumber.Numberisanyinteger.
-
nolog
Blockslogfilegeneration.
-
sdfnowarn
DonotdisplaySDFwarnings.
-
sdfnoerror
TreaterrorsfoundinSDFfileaswarnings.
-
sdfmin|
-
sdftyp|
-
sdfmax
<
root=file
>
SpecifiesthetypeofdelaysISimshoulduse.
-
sdfmin
-SDFannotates<file>at<root>withminimum
delay.
-
sdftyp
-SDFannotates<file>at<root>withtypical
delay.
-
sdfmax
-SDFannotates<file>at<root>with
maximumdelay.
-
sdfroot
<
root_path
>
SetsdefaultplaceinthedesignhierarchywhereSDF
annotationisapplied.
-
tclbatch
<
file_name
>
Turnbatchmodeon. Bydefaultbatchmodeisoff.When
batchmodeoff,Tclcommandscanbeissuedfromthe
Consolepaneleveniftheengineisbusysimulating.When
batchmodeison,allofthecommandsinthespecifiedbatch
fileareexecutedsequentiallyuntilcompletion,ignoringany
commandsenteredfromthecommandprompt.file_name
specifiesthenameoffilecontainingTclcommandstobe
executed.
ForinformationaboutISimTclcommands,seeSimulation
CommandOverview.
-
testpusarg
<
string|stringvalue
>
Whenthesimulatormatchesthiscommandlineargument
stringwiththe$test$plusargor$value$plusargsystem
functionofaVerilogdesignfile,thetestordesignbehavior
changeassociatedwiththesystemfunctionisrun.
stringisanystring.Forexample,
-
testplusarg
HELLO
.
IfaVerilogfileuses($test$plusargs("HE")),thefunction
willreturntrue.
stringvalueisanappropriatestringfortheVerilogformat
specifiers. Itprovidesavaluetothevariableinthe
$value$plusargssystemfunctioncall. Forexample,
-
testplusarg
FINI
S
H=10000
. IfaVerilogfileuses
($value$plusargs("FINISH=%d",stop_clock))andwhen
Verilogformatspecifier%dmatches10000,andstop_clock
willgetvalue10000andthefunctionwillreturntrue.
Thesamestringorstringandvalueneedtobesetbothin
thiscommandlineswitchandinthesystemfunctionforthe
actionspecifiedintheVerilogfile(suchasavaluedisplay)
tooccur.
-
vcdfile
<
vcd_file
>
SpecifiestheVCDoutputfileforVerilogprojects.Default
filenameis
dump
.
vcd
.
-
vcdunit
<
unit
>
SpecifiestheVCDoutputtimeunit.Possiblevaluesare
fs
,
ps
,
ns
,
us
,
ms
and
sec
.Defaultis
ps
.
-
view
<
waveform_file.wcfg
>
Usedincombinationwiththe
-
gui
switchtoopenthe
specifiedwaveformfileintheISimgraphicuserinterface.
-
wdb
<
waveform_database_file.wdb
>
Simulationdataissavedtothespecifiedfile.Forexample:
x
.
exe
wdb my
.
wdb
savesthesimulationdatato
my
.
wdb
insteadofthedefault
isimgui
.
wdb
.
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Append
i
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:
Re
f
erence
I
S
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mS
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t
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onExecu
t
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eExamp
l
es
TheISimsimulationexecutablecommandcanbeusedasfollows.
Torunthesimulationexecutablenamed
watchvhd
inbatchmode:
watchvhd
.
exe
-
tclbatch batchfile
Torunthesimulationexecutablenamed
watchvhd
withback-annotationusingthedelayinformationinthe
file
adder
.
sdf
:
watchvhd
.
exe
-
sdftyp adder
.
sdf
Torunthesimulationexecutableinteractively:
watchvhd
.
exe
TorunthesimulationintheISimGUI:
watchvhd
.
exe
gui
Togetclocktoterminatesimulationifspecified.
AVerilogfilecontainsthefollowing:
real frequency
;
reg [
8*32:1
] testname
;
integer stop_clock
;
if
($
value
$
plusargs
("FINISH=%
d
",
stop_clock
))
begin
repeat
(
stop_clock
) @(
posedge clk
);
$
finish
;
end
Enter:
x
.
exe
-
testplusarg
FINI
S
H=10000
f
use
f
useOverv
i
ewandSyn
t
ax
No
t
e
Thefollowinginformationisintendedforadvancedusers.
ThefusecommandistheHardwareDescriptionLanguage(HDL)compiler,elaboratorandlinkerusedbythe
ISim.Thecommandlinksdesignunitsalreadycompiledwithvhpcomporvlogcomp,andcreatesasimulation
executable. Italsotakesamixedlanguageprojectfileandcompilesthedesignunitsonthefly.Name(s)ofthe
top-leveldesignunit(s)mustbespecifiedonfusecommandlineargument. Thefusecommandeffectsstatic
elaborationonthedesigngiventhetopdesignunitsandthencompilesthedesignunitstoobjectcode.Thedesign
unitobjectcodesarethenlinkedtogethertocreateasimulationexecutable.
Useoneormoretopleveldesignunitnamesas{[<library_name>.]<top_name>}. Forexample,designunit
nameofthetestbenchfile.IfthedesignusesaVerilogUNISIMorVerilogSIMPRIMlibrary,onetopname
mustbe
glbl
.Includingalibrarynameisoptional.Thedefaultlibraryname
work
isassumedwhena
librarynameisnotspecified.
Usethe
-
prj
optiontocallvhpcomporvlogcomp,asappropriate,andtocompileyourHDLcode.
Usethe
-
o
<
sim_exe
>
optiontochangesthesimulationexecutablefilenameandlocationfromthedefault
x
.
exe
.
Thefusecommandgeneratesobjectcodeanddatafilesforeachdesignunitcomprisingthedesignandplaces
theminside
isim
/<
simulation_executable
>.
sim
directory.
No
t
e
Donoremovethe
isim
/<
simulation_executable
>.
sim
directoryotherwisethedesigncannotbe
simulated.
Thesyntaxforthiscommandisasfollows:
fuse
(
option
)
I
S
i
m User
G
u
i
de
12
0
www.x
ili
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U
G
660(v11.
3
)
Sep
t
ember16,2
00
9
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