pdf viewer control without acrobat reader installed c# : Add image to pdf file acrobat Library SDK component .net asp.net web page mvc plugin_ism12-part2692

Append
i
x
:
Re
f
erence
whereoptionisanyoptionfoundinfuseOptions.
No
t
e
Thiscommandiscasesensitive.
f
useOp
t
i
ons
The
fuse
commandoptionsareasfollows.
-
d <macro_definition> > [
=
<value> ]
ThisoptionisforVerilogonly.Definethemacrosusedin
Verilogfiles,andanyvaluetheyrequire.Morethanone
-
d
canbespecified.
No
t
e
Thereshouldbenospacebetweenthe"
=
"andthe
valueasthisspacewouldbeinterpretedaspartofthevalue.
-
f <cmd_file>
Youcansavefusecommandoptionsinatextfileforfuture
use.Thisoptionreadsandexecutesthesavedoptions,
specifiedincmd_file.
-
generic_top
"
<parameter>
=
<value>
"
Overridesgenericorparameterofatopleveldesignunit
withthespecifiedvalue.Forexample,
-
generic_top
“P=10”
wouldapplythevalueof10ontoplevelparameter
Pbeforeelaboration.
-
h
Displaysallcommandlineoptionsandtheirusage.
-
i <include_path>
ThisoptionisforVerilogonly.Specifiesthatiffusecalls
vlogcomp,itshouldusethespecifiedpathforVerilog
’includedirectives.Each
-
i
canbeusedforonlyoneinclude
path.Morethanone
-
i
canbespecified. Placequotes
aroundpathswithspaces.
-
incremental
Compilesonlythefilesthathavechangedsincelastcompile.
-
initfile <sim_init_file>
Specifiesauserdefinedsimulatorinitfiletoaddtoor
tooverridethelogical-to-physicalmappingsoflibraries
providedbythedefault
xilinxsim
.
ini
file.
-
intstyle
ise | | xflow w | silent
Useoneofthespecifiedstylesforprintingmessages.
Specify
ise
toprintmessagesfortheISEConsoleor
xflow
toprintmessagesforXFLOW.Specify
silent
tosuppress
allmessages. Bydefaultallmessagesareprinted.
-
ise <file>
EnablesyoutospecifyaXilinxISEfile.
-L
|
-
lib <search_lib> > [
=
<lib_path> ]
Specifiesotherlibrariesandoptionallythephysical
pathnameforthoselibraries.Multiple
-L
canbeused,
andaretreatedasresourcelibraries. Thephysicalpath
providedthrough
-L
overridesmappingsprovidedbythe
xilinxsim
.
ini
file.
Search_libisthelogicalnameofthespecifiedlibrary
optionallyfollowedbythelib_path,thepathtothephysical
library. Forexample:
-L
mylib
=C:
home
/
mylib
ForVerilogdesigns,fusesearchesforlibrariesintheorder
thatthe
-L
optionsarecoded.Forexample:
fuse
-L
unisim
-L
abcsim
-L
xyzsim mytop
First,fusesearchesfordesignunitsinUNISIM,andthen
abcsim, andxyzsim.Ifadesignunitwasdefinedinabcsim
aswellasinxyzsim,theoneinabcsimwouldbeusedas
thatappearsbeforexyzsim.
Iftheorderwaschangedto:
fuse
-L
unisim
-L
xyzsim
-L
abcsim mytop
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Add image to pdf file acrobat - insert images into PDF in C#.net, ASP.NET, MVC, Ajax, WinForms, WPF
Sample C# code to add image, picture, logo or digital photo into PDF document page using PDF page editor control
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Append
i
x
:
Re
f
erence
Andbothxyzsimandabcsimdefinedthesamedesignunit,
fusewouldpickthedesignunitfromxyzsim.
-
maxdelay
ThisoptionisforVerilogonly.Specifiesthatiffusecalls
vlogcomp,itshoulduseworstcasedelays.
-
maxdesigndepth <depth>
Overridesmaximumdesigndepthallowedbythe
elaborator.Ifadesignexceedsthedepth,elaboratorwould
errorout. Maybeusedtoincreasethedepthincasethe
elaboratorfalselythinksthatadesignhasinfiniterecursive
instantiation.
-
mindelay
ThisoptionisforVerilogonly.Specifiesthatiffusecalls
vlogcomp,itshouldusefastestpossibledelays.
-
mt <value>
Specifiesthenumberofsub-compilationjobswhichcan
beruninparallel. Possiblevaluesare
on
,
off
,oran
integergreaterthan1.Defaultison,wherethecompiler
automaticallychoosesanumberbasedonnumberofcores
inthesystem.
-
nodebug
Generatesoutputthathasnoinformationfordebugging
yourHDLcodeduringsimulation.Outputwithnodebug
informationrunssimulationfaster. Thedefaultisto
generateHDLunitsfordebugging.
-
nospecify
ThisoptionisforVerilogonly. Disablesspecifyblock
functionality.
-
notimingchecks
ThisoptionisforVerilogonly.Disablesthetimingchecks.
-
o <sim_exe>
Specifiesthenameofthesimulationexecutableoutputfile.
Thenameofthefileissim_exe.Ifyoudonotusethisoption,
thedefaultexecutablenameis:
work_lib
/
mod_name
/
platform
/
x
.
exe
where:
work_libistheworklibrary.
mod_nameisthefirsttopmodulespecified.
platformisWindows.
-
override_timeprecision
Overridesthetimeprecision(unitofaccuracy)ofallVerilog
modulesinthedesignwiththetimeprecisionspecifiedin
the
-
timescale
option.
-
override_timeunit
Overridesthetimeunit(unitofmeasurementofdelays)
ofallVerilogmodulesinthedesignwiththetimeunit
specifiedinthe
-
timescale
option.
-
prj <prj_file>
.
prj
Specifiesaprojectfiletouseforinput. Aprojectfile
containsalistofallthefilesassociatedwithadesign.Itis
themainsourcefileusedbytheISE®software.
Prj_fileistheprojectfileandmusthavea
prj
extension.
-
rangecheck
ThisoptionisforVHDLonly.Specifiesvaluerangecheckto
beperformedonVHDLassignments.
No
t
e
Thisoptiondoesnotaffectindexrangecheckingfor
arrays.ISimalwayschecksanindexintoanarrayforbeing
withintheallowedrange.
Bydefault
-
rangecheck
itisturnedoff.
-
sourcelibdir
Specifiesthesourcedirectoryforlibrarymodules.Formore
informationandexamples,seeSupportingSourceLibraries.
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.NET PDF Document Viewing, Annotation, Conversion & Processing
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Append
i
x
:
Re
f
erence
-
sourcelibext
Specifiesthefileextensionforsourcefilesformodules.The
sourcelibdir
optionprovidesthelocationforthese
files.Formoreinformationandexamples,seeSupporting
SourceLibraries.
-
sourcelibfile
Specifiesthefilenameforlibrarymodules. Formore
informationandexamples,seeSupportingSourceLibraries.
-
timeprecision_vhdl<time_precision>
Specifiesthetimeprecision(unitofaccuracy)forallVHDL
designunits.
Thetime_precisionisenteredasnumber(1|10|100|...)
followedbyunit(fs|ps|ns|us|ms|s).
Thedefaultis1ps.
-
timescale <time_unit
/
time_precision>
SpecifiesthedefaulttimescaleforVerilogmodulesthatdo
nothaveaneffectivetimescale.Thetime_unitistheunit
ofmeasurementofdelays.Thetime_precisionistheunitof
accuracy.
Bothtime_unitandtime_precisionareenteredasnumber
(1|10|100|...)followedbyunit(fs|ps|ns|us|ms|s).
Thedefaulttimescaleis1ns/1ps.
-
typdelay
ThisoptionisforVerilogonly.Specifiesthatiffusecalls
vlogcomp,itshouldusetypicaldelays.
-
v <value>
Specifiestheverbositylevelforprintingmessages.Allowed
valuesare0,1,or2.Thedefaultis0.
fuse-v1printsusefuldebugginginformation,whichcan
helptoidentifyproblemsinISimcompilers.
DumpsthelibrarymappingasseenbyISimcompiler
afterreadingallavailablelibrarymappingfiles
(
xilinxsim
.
ini
)
Getsverbosemessagesfromdesignelaborator
Getsthedumpsofcurrentvaluesofenvironment
variableswhichaffectthebehavioroftheISimcompiler
GetsthelistofloadedsharedobjectsbytheISim
compiler
Dumpsoperatingsysteminformation,includingversion
numberandprocessor
DumpspathtoGCCcompilerbeingusedtocompilethe
generatedcode
-
version
Printsthecompilerversion.
f
useExamp
l
es
Us
i
ngP
recomp
il
ed
H
D
L
ThefollowingexamplesshowhowtoinvokefuseusingprecompiledHDL.
ForVHDLusingatoplevelconfiguration:
fuse work
.
yourtop
ForVerilogormixedlanguagedesignusingallofthetoplevelmodules:
fuse work
.
top_level_module_name_
1
work
.
top_level_module_name_
2
work
.
glbl
-L
simprims_ver
-L
logical
L
ib
1 -
o mysim
.
exe
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C# Windows Viewer - Image and Document Conversion & Rendering in
conversion library toolkit in C#, you can easily perform file conversion from Image and Document Conversion Supported by Windows Viewer. Convert to PDF.
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may easily achieve the following PowerPoint file conversions SDK to convert PowerPoint document to PDF document demo code for PowerPoint to TIFF image conversion
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Append
i
x
:
Re
f
erence
Us
i
ng
H
D
LSou
rce
ExampleoffuseinvokedusingsourceVHDL
Thisexampleproducesanexecutablecalled
tb
.
exe
fromVHDLsourcelistedintheprojectfilecalled
x
.
prj
.
Thecontentsoftheprojectfileareasfollows:
V
HDL
work x
1.
vhd
V
HDL
work x
2.
vhd
V
HDL
work x
3.
vhd
V
HDL
work tb
.
vhd
fuse
-
prj x
.
prj work
.
tb_top
-
o tb
.
exe
Tostartsimulation,executethefollowing:
tb
.
exe
ExampleoffuseinvokedusingsourceVerilog
Thisexampleproducesanexecutablecalled
tb
.
exe
fromVerilogsourcelistedintheprojectfilecalled
myproj
.
prj
.Thetopleveldesignunitistbdefinedinfile
tb
.
v
.Thecontentsof
myproj
.
prj
areasfollows:
Verilog work x
1.
v
Verilog work x
2.
v
Verilog work x
3.
v
Verilog work tb
.
v
Usethefollowingcommandtorunfuse:
fuse
-
prj myproj
.
prj work
.
tb work
.
glbl
-
o tb
.
exe
Tostartsimulation,executethefollowing:
tb
.
exe
No
t
e
ForVerilog,ifthedesigninstantiatesanymodulesthathavebeencompiledintoanylibrariesotherthan
theworklibrary,thoselibrariesmustbepassedtofuseusingthe
-L
commandlineoptionsothatfusewillfind
thosedesignunitsandlinkthemintothesimulationexecutable.
ExampleoffuseinvokedusingmixedVHDL/Verilogdesign
Thisexampleproducesanexecutablecalled
tb
.
exe
fromVerilogandVHDLsourcecodelistedintheprojectfile
called
myproj
.
prj
.Therearetwotopleveldesignunits:aVHDLtoplevelcalledtbandaVerilogtoplevelunit
calledglbldefinedin
tb
.
vhd
and
glbl
.
v
respectively.Thecontentsof
myproj
.
prj
areasfollows:
Verilog work x
1.
v
V
HDL
work x
2.
vhd
Verilog work x
3.
v
V
HDL
work x
4.
vhd
Verilog work glbl
.
v
V
HDL
work tb
.
vhd
Usethefollowingcommandtorunfuse:
fuse work
.
tb work
.
glbl
-
prj x
.
prj
-
o tb
.
exe
Tostartsimulation,executethefollowing:
tb
.
exe
No
t
e
ForMixedlanguagedesigns,forthemodulesonlanguageboundaryandfortheVerilogmodulesthat
havebeencompiledintoanylibrariesotherthantheworklibrary,thoselibrariesmustbepassedtofuseusingthe
-L
commandlineoptioninthedesiredsearchordersothatfusewillfindthosedesignunitsandlinktheminto
thesimulationexecutable. Formoreinformation,seeMixedLanguageSimulationOverview.
Us
i
ng
t
he
C
ommand
Fil
eOp
t
i
on
Thefollowingexampleshowshowtoinvokefuseusingthe
-
f
option:
fuse
-
f my_design
.
cmd
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C# Word - Word Conversion in C#.NET
you may easily achieve the following Word file conversions. XDoc.Word SDK to convert Word document to PDF document C# demo code for Word to TIFF image conversion
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VB.NET PDF: How to Create Watermark on PDF Document within
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Append
i
x
:
Re
f
erence
ThefollowingisanexampleofacommandfileforVerilog:
-
nodebug
-
intstyle xflow
-
incremental
top_level_module_name_
1
top_level_module_name_n
-L
logical
L
ib
1
-L
logical
L
ib
2
v
l
ogcomp
v
l
ogcompOverv
i
ewandSyn
t
ax
No
t
e
Thefollowinginformationisintendedforadvancedusers.
TheVerilogcompiler,vlogcomp,isusedbytheISimtoparseVerilogsourcefilesandgenerateobjectcodefor
alldesignunitsinthosefiles. Theobjectcodegeneratedbyvlogcompisusedbyfusetocreateasimulation
executable.
YoumustspecifyeitheraprojectfileoroneormoreVerilogsourcefilestocompile. Ifneithertheprojectfilenor
theVerilogfileisspecified,vlogcompissuesanerror.
Thesyntaxforthiscommandisasfollows:
vlogcomp
(
option
)
whereoptionisanyoptionfoundinvlogcompOptions.
No
t
e
Thiscommandiscasesensitive.
v
l
ogcompOp
t
i
ons
The
vlogcomp
commandoptionsareasfollows.
<verilog_file>
SpecifiestheVerilogfiletobecompiled.
-
d <macro_definition> > [
=
<value>]
DefinethemacrosusedinVerilogfiles,andanyvaluethey
require.Morethanone
-
d
canbespecified
-
f <cmd_file>
Youcansavevlogcompcommandoptionsinatextfile
forfutureuse.Thisoptionreadsandexecutesthesaved
options,specifiedincmd_file.
-
h
Displaysallcommandlineoptionsandtheirusage.
-
i <include_path>
SpecifiespathforVerilog’includedirectives.Morethanone
-
i
canbespecified.
-
incremental
Compilesonlythefilesthathavechangedsincelastcompile.
-
initfile<sim_init_file>
Specifiesthephysicalpathtouserdefinedsimulatorinitfile
insteadofdefault
xilinxsim
.
ini
file.
-
intstyle
ise |xflow w |silent
Useoneofthespecifiedstylesforprintingmessages.Specify
ise
toprintmessagesfortheISEConsoletabor
xflow
to
printmessagesforXFLOW.Specify
silent
tosuppressall
messages. Bydefaultallmessagesareprinted.
-
ise <file>
EnablesyoutospecifyaXilinxISEfile.
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5
VB.NET PowerPoint: VB Code to Draw and Create Annotation on PPT
as a kind of compensation for limitations (other documents are compatible, including PDF, TIFF, MS VB.NET PPT: VB Code to Add Embedded Image Object to
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Append
i
x
:
Re
f
erence
-L
|
-
lib
<
search_lib> [
=
<lib_path>]
Specifiesotherlibrariesandoptionallythephysicalpath
nameforthoselibraries.Multiple
-
lib
optionscanbeused,
andaretreatedasresourcelibraries. Thephysicalpath
providedthrough
-
lib
overridesthemappingsprovided
bythe
xilinxsim
.
ini
file.
Search_libisthelogicalnameofthespecifiedlibrary
optionallyfollowedbythelib_path,thepathtothephysical
library.Forexample:
-
lib mylib
=C:/
home
/
mylib
-
maxdelay
Specifiesthatvlogcompshoulduseworstcasedelays.
-
mindelay
Specifiesthatvlogcompshouldusefastestpossibledelays.
-
nodebug
Generatesoutputthathasnoinformationfordebugging
yourHDLcodeduringsimulation.Outputwithnodebug
informationrunssimulationfaster.Defaultistogenerate
HDLdebugunits.
-
nospecify
IgnoresVerilogpathdelaysandtimingchecks.
-
notimingchecks
IgnorestimingcheckconstructsinVerilogspecifyblocks.
-
prj <prj_file>
.
prj
Specifiesaprojectfiletouseforinput. Aprojectfile
containsalistofallthefilesassociatedwithadesign.Itis
themainsourcefileusedbytheISE®software.prj_fileisthe
pathtotheprojectfileandtheprojectfilenamewitha
.
prj
extension.Youcanincludeanabsoluteorrelativepathtothe
projectfile.Forarelativepath,include../aspartofthepath.
-
sourcelibdir
Specifiesthesourcedirectoryforlibrarymodules.Formore
informationandexamples,seeSupportingSourceLibraries.
-
sourcelibext
Specifiesthefileextensionforsourcefilesformodules.The
sourcelibdir
optionprovidesthelocationforthese
files.Formoreinformationandexamples,seeSupporting
SourceLibraries.
-
sourcelibfile
Specifiesthefilenameforlibrarymodules. Formore
informationandexamples,seeSupportingSourceLibraries.
-
typdelay
Specifiesthatvlogcompshouldusetypicaldelays.
-
v <value>
Specifiestheverbositylevelforprintingmessages.Allowed
valuesare0,1,or2.Thedefaultis0.
-
version
Printsthecompilerversion.
-
work <work_lib> > [
=
<lib_path>]
Specifiesthe
work
library,andoptionally,thephysical
pathfortheworklibrary. Thephysicalpathprovided
throughthisoptionoverridesmappingsprovidedbythe
xilinxsim
.
ini
file.Thedefaultworklibraryisthelogical
library
work
.
Work_libisthelogicalnameofthespecified worklibrary
optionallyfollowedbylib_path,thepathtothephysical
library.Forexample:
mywork
=C:/
home
/
worklib
v
l
ogcompExamp
l
es
The
vlogcomp
commandcanbeusedasfollows.
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PDF to WORD Converter | Convert PDF to Word, Convert Word to PDF
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Append
i
x
:
Re
f
erence
ToinvoketheVerilogcompilerwithalloptionssavedinafilecalled
run
32.
txt
:
vlogcomp
-
f run
32.
txt
ToinvoketheVerilogcompilerusingaworklibrarywiththelogicalnamemysimworklocatedinthe
/
home
/
smithjj
/
mylib
directory,andcompilealltheVerilogfilesintheprojectfile
dsp
64.
prj
:
vlogcomp
-
work mysimwork
=/
home
/
smithjj
/
mylib
-
prj dsp
64.
prj
ToinvoketheVerilogcompilerusingthedefaultworklibraryspecifiedinthe
xilinxsim
.
ini
fileandcompile
theVerilogfiles
suba
.
v
and
subb
.
v
:
vlogcomp suba
.
v subb
.
v
vhpcomp
vhpcompOverv
i
ewandSyn
t
ax
No
t
e
Thefollowinginformationisintendedforadvancedusers.
TheVHDLcompiler,vhpcomp,isusedbyISimtoparsesVHDLsourcefilesandgenerateobjectcodeforall
designunitsinthosefiles. Theobjectcodegeneratedbyvhpcompisusedbyfusetocreateasimulation
executable.
YoumustspecifyeitheraprojectfileoroneormoreVHDLfilestocompile. IfneitherprojectfilenorVHDLfile
arespecified,vhpcompissuesanerror.
Thesyntaxforthiscommandisasfollows:
vhpcomp
(
option
)
whereoptionisanyoptionfoundinvhpcompOptions.
No
t
e
Thiscommandiscasesensitive.
vhpcompOp
t
i
ons
The
vhpcomp
commandoptionsareasfollows.
<vhdl_file>
SpecifiesoneormoreVHDLsourcefilestobecompiled.
-
f
<
cmd_file
>
Youcansavevhpcompcommandoptionsinatextfile
forfutureuse.Thisoptionreadsandexecutesthesaved
options,specifiedincmd_file.
-
h
Displaysallcommandlineoptionsandtheirusage.
-
incremental
Compilesonlythefilesthathavechangedsincelastcompile.
-
intstyle
ise | | xflow w | silent
Useoneofthespecifiedstylesforprintingmessages.Specify
ise
toprintmessagesfortheISE®softwareConsoletabor
xflow
toprintmessagesforXFLOW.Specify
silent
to
suppressallmessages. Bydefaultallmessagesareprinted.
-
ise <file>
EnablesyoutospecifyaXilinxISEfile.
-L
|
-
lib
<
search_lib> [
=
<lib_path>]
Specifiesotherlibrariesandoptionallythephysicalpath
nameforthoselibraries.Multiple
-
lib
optionscanbeused,
andaretreatedasresourcelibraries. Thephysicalpath
providedthrough
-
lib
overridesthemappingsprovided
bythe
xilinxsim
.
ini
file.
Search_libisthelogicalnameofthespecifiedlibrary
optionallyfollowedbythelib_path,thepathtothephysical
library.Forexample:
-
lib mylib
=C:/
home
/
mylib
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www.x
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12
7
Append
i
x
:
Re
f
erence
-
nodebug
Generatesoutputthathasnoinformationfordebugging
yourHDLcodeduringsimulation.Outputwithnodebug
informationresultsinafastersimulationruntime.Default
istogenerateHDLdebugunits.
-
prj <prj_file>
.
prj
Specifiesaprojectfiletouseforinput. Aprojectfilecontains
alistofallthefilesassociatedwithadesign.Itisthemain
sourcefileusedbytheISEsoftware.Prj_fileisthepathtothe
projectfileandtheprojectfilenamewitha
.
prj
extension.
Youcanincludeanabsoluteorrelativepathtotheproject
file.Forarelativepath,include../aspartofthepath.
-
rangecheck
Enablesruntimevaluerangecheck(VHDLonly). This
optioncausesvhpcomptogenerateoutputthatchecksthat
valuesassignedtoVHDLsignalsarewithintheirvalid
range. Forexample,ifasignalisdeclaredaspositive,fuse
willcheckthatthesignalisnotassignedanegativenumber.
Orifasignalisdeclaredasstd_logic,vhpcompgenerates
outputtocheckthatthesignalisassignedonlyvalid
std_logicvalues(U,X,0,1,Z,W,L,H,-).
No
t
e
Thisoptiondoesnotaffectthecheckingofindex
ranges.ISimalwayscheckstherangesofindexes.
Bydefault
-
rangecheck
isturnedoff.
-
v <value>
Specifiestheverbositylevelforprintingmessages.Allowed
valuesare0,1,or2.Thedefaultis0.
-
work <work_lib> > [
=
<lib_path>]
Specifiestheworklibrary,andoptionally,thephysical
pathfortheworklibrary. Thephysicalpathprovided
throughthisoptionoverridesthemappingsprovidedby
the
xilinxsim
.
ini
file.Thedefaultworklibraryisthe
logicallibrary
work
.
Work_libisthelogicalnameofthespecifiedworklibrary
optionallyfollowedbylib_path,thepathtothephysical
library.Forexample:
mywork
=C:/
home
/
worklib
vhpcompExamp
l
es
The
vhpcomp
commandcanbeusedasfollows.
ToinvoketheVHDLcompilerwithalloptionssavedinafilecalled
run
32.
txt
:
vhpcomp
-
f run
32.
txt
ToinvoketheVHDLcompilerusingaworklibrarywiththelogicalname
mysimwork
locatedinthe
/
home
/
smithjj
/
mylib
directory,andcompilealltheVHDLfilesintheprojectfile
dsp
64.
prj
:
vhpcomp
-
work mysimwork
=/
home
/
smithjj
/
mylib
-
prj dsp
64.
prj
ToinvoketheVHDLcompilerusingthedefaultworklibraryspecifiedinthe
xilinxsim
.
ini
fileandcompile
theVHDLfiles
suba
.
vhd
and
subb
.
vhd
:
vhpcomp suba
.
vhd subb
.
vhd
Th
i
r
d-Part
y
C
ommandEqu
i
va
l
ency
Th
i
r
d-Part
yS
i
mu
l
a
t
i
on
C
ommandSuppo
rt
Overv
i
ew
ISimdoesnotsupportthird-partycommands.IfsimulationcommandsinaDO(*.do)fileareusedinISim,ISim
willnotunderstandthecommandsunlessthereisanexactISimequivalentcommand,suchas
run
).
I
S
i
m User
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u
i
de
12
8
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ili
nx.com
U
G
660(v11.
3
)
Sep
t
ember16,2
00
9
Append
i
x
:
Re
f
erence
YoucanmapyourDOfilecommandstoISimcommandsusingtheinformationbelow:
Third-PartyCompilerCommands
Third-PartyTclCommands
Th
i
r
d-Part
y
C
omp
il
erC
ommands
UsethefollowingtableasguidancewhenmappingyourDOfilecompilationcommandstoISimcommands.
C
omp
il
erC
ommand
C
ompa
t
i
b
ili
t
yTab
l
e
D
O
Fil
e
C
ommand
I
S
i
m
C
ommand
Remarks
vcom
-
work
<libname>
-93
<file_name>
vhpcomp
<file_name>
CompilesVHDLfile.
vlog
-
work
<libname><file_name>
vlogcomp
<file_name>
Compilesverilogfile.
vsim
<lib_name>
.
<design_name>
fuse
-
lib
<lib_name><design_name>
Buildsasimulationexecutable.
vsim
<lib_name>
.
<design_name>
<mti.do>
<executable_name>.exe
-
tclbatch
<design_name>
.
tclbatch
Runssimulation.
vsim
[
-
sdfmin
|
-
sdftyp
|
-
sdfmax
][<instance>
=
]<sdf_filename>]
[
-
sdfnoerror
][
-
sdfnowarn
]
[
+
sdf_verbose
]
sdfcommandscanonlybeinvoked
ascommandargumentstovsim
commands.
sdfanno
{
-
min|
-
typ|
-
max
}
<file_name>[
-
nowarn
][
-
noerror
]
[
-
root
<path_name>]
SDFannotation.
Th
i
r
d-Part
yTc
l
C
ommands
UsethefollowingtableasguidancewhenmappingyourDOfilesimulationcommandstoISimcommands.
S
i
mu
l
a
t
i
onTc
l
C
ommand
C
ompa
t
i
b
ili
t
yTab
l
e
D
O
Fil
e
C
ommand
I
S
i
m
C
ommand
Remarks
add
[
wave
]
-
recursive
<
item_name
>
[
-
ports
|
-
in
|
-
out
|
-
inout
]ordeletecommand
selectsthenetstobetraced.
wave add
or
ntraceselect
-
o
{
on
|
off
}
-
m
<module_name>
-
l
{
all
|
this
}[
-
n
<net_name>]
Selectsmodulesandsignalsfortracing
duringsimulation.
-
o
turnstracingon
oroffonaspecifiedmoduleorsignal.
ThiscommandisforGUIsignaltrace
only.
Ignoredoptions: AllGUIoptions
associatedwith
add wave
,suchas
-
divider
and
-
scale
.
bd
id#1ormorecanbespecified.
bpdel
<index>[<index>...]
Removesbreakpointbasedonthe
indexwheretheindexistheindex
numberassignedtothebreakpoint
youwanttodelete.Eachbreakpointin
yourdesignisassignedauniqueindex
number.
bd
<file_name><line_number>
bpremove
<file_name><line_number>
Removesbreakpointat<line_number>
in<file_name>.
bd
<file_name><line_number> |<id#>
bpremove
<file_name><line_number>
Removesbreakpointat<line_number>
in<file_name>.
bp
<file_name><line_number>
bpadd
<file_name><line_number>
Addsbreakpointat<line_number>in
<file_name>. Ignoredoptions:[
-
id
<id#>],[
-
inst
<region>],[
-
cond
{<condition_expression>}]
I
S
i
mUser
G
u
i
de
U
G
660(v11.
3
)
Sep
t
ember16,2
00
9
www.x
ili
nx.com
12
9
Append
i
x
:
Re
f
erence
D
O
Fil
e
C
ommand
I
S
i
m
C
ommand
Remarks
bp
-
query
<file_name>
bplist
Listsallbreakpoints.
delete wave
ntrace
-
o off
Turnstracingoffforaspecifiedmodule
orsignal.
drivers
<itemname>
show driver
<net_name>
Showsallthedriversthataredriving
thespecified<net_name>.
env
scope
Displayswhereyouareinthedesign
hierarchy.
env
..
scope
..
Changestotheparentofcurrentscope.
env
<pathname>
scope
path_name
Changestothescopespecifiedby
<path_name>
Ignoredoptions:
-
nodataset
,
-
dataset
.
examine
<signal_name>
show value
<signal_name>
Showsthevalueofasignal.
exit
exit
Exitsthesimulator.
force
-
deposit
<signal_name>
<value>[<time>]
put
Changesthevaluetonewvalue,but
thenewvaluegetsoverwrittenby
assignmentsmadeinHDL.
force
-
freeze
isim force add
Overridesallassignmentsdonefrom
HDL,andmakesthesignal/wiretruly
stuckorfrozenataparticularvalue.
help
help
DisplaysallTclcommandsandtheir
usage.
help
[command|topic]
help
<command>
Displayshelpinfoonacommand.
if
{[
exa sig_a
]
== "0011
ZZ
"
}
{
echo
"
Signal value matches
"
}
test
<signal_name><value>
Teststhesignalvaluedisplayifitis
different.
noforce
<signal>
isim force remove
<signal>
Removesavalueonasignal. This
commandforcesavalueonthesignal,
untilisimforceremoveisissued.
ThiscommandworksonlyforVHDL
signalsandVerilogwiretypes.Itdoes
notworkforVerilogregs.
quit
quit
ExitsTclprompt.
Ignoredoptions: [
-
f
|
-
force
]
[
-
sim
].
radix
isim get radix
Returnsthedefaultradixasastring
inTclresultvariable,anddisplaysthe
defaultradixtostdout.
radix
-
<radix_type>
isim get radix
<radix_type>
Setstheglobalradixforthecurrent
simulation.
restart
restart
Stopssimulationandsetssimulation
timebackto0.
run
<length><unit>
run
<length><unit>
Runssimulationfor<length><unit>
time.
run
-
all|
-
continue
run
{
all
|
continue
}
Runssimulationuntilthereareno
moreevents.
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m User
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i
de
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3
0
www.x
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nx.com
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G
660(v11.
3
)
Sep
t
ember16,2
00
9
Documents you may be interested
Documents you may be interested