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Chapter3
VHDLSimulation
V
H
D
LS
i
mu
l
a
t
i
onOverv
i
ew
Runningasimulationfromthecommandlineinvolvesthreebasicsteps:
1. Parsingthedesignfiles
2. GeneratingtheISimsimulationexecutable
3. Simulatingthedesign
Gototheappropriatesimulationtopicfordetails:
RunningaFunctionalSimulationattheCommandLine
RunningaTimingSimulationattheCommandLine
Runn
i
nga
F
unc
t
i
ona
l
S
i
mu
l
a
t
i
ono
f
aV
H
D
L
D
es
i
gn
F
r
om
t
he
C
ommandL
i
ne
Me
t
hod1
:
Us
i
ngaP
r
o
j
ec
t
Fil
e-Recommended
ParsingtheDesignFiles
Createafilecalled
<
proj_name
>.
prj
andusethefollowingsyntaxinsidetheprojectfile:
vhdl
<
library_name
> <
file_name_
1>.
vhd
vhdl
<
library_name
> <
file_name_
2>.
vhd
.
vhdl
<
library_name
> <
file_name_n
>.
vhd
where:
<library_name>indicatesthelibraryintowhichthesourceonthegivenlineshouldbecompiled.
<library_name>isoptionalandisonlyneededwhenusingadifferentlibrarythanthedefault
work
.
<file_name_1>.vhdisthesourcefile.EachlinecancontainonlyoneVHDLsourcefile.
Exampleoffilecalled
project_name
.
prj
:
vhdl work top
.
vhd
vhdl mylib_for_testbench testbench
.
vhd
No
t
e
Thetoplevelfile
testbench
.
vhd
containstheentitynamedtestbench.
GeneratingtheISimSimulationExecutable-Runningfuse
TheHDLlinker,fuse,performsstaticelaborationofadesignintermsofparsednodes,generatesobjectcode
foreachuniquemoduleinstance,andlinksthegeneratedobjectcodeswiththeISimsimulationenginelibrary
tocreateanISimsimulationexecutable.
Syntax:
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Chap
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:
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on
fuse {[<library_name>
.
]<top_name>}
-
prj <prj_file_name>.prj
-
o <output_file_name>
where:
{[<library_name>.]<top_name>}isoneormorelibrariesandtopleveldesignunitnames. <library_name>is
optionalandisonlyneededwhenusingadifferentlibrarythanthedefault
work
.Ifspecified,theHDLfile
thatcontainsthetoplevelhastobecompiledintherelatedlibrarynameasreferredintheprojectfile. For
example,designunitnameofthetestbenchfile.
-
o
switchisoptionalfordefiningtheisimexecutablename. Without
-
o
,thedefaultnamefortheisim
executableis
x
.
exe
.
Examplefusecommandwithprojectfile:
fuse mylib_for_testbench
.
testbench
-
prj project_name
.
prj
SeefuseOverviewandSyntaxformoreinformationaboutthefusecommand.
Me
t
hod2
:
Pars
i
ng
t
he
Fil
esUs
i
ngvhpcomp
ParsingtheDesignFiles
Syntax:
vhpcomp [
-
work] <library_name> > <file_name>
.
vhd
where
-
work
isoptionalandisonlyneededwhentryingtospecifyadifferentlibrarythanthedefaultwork.
<library_name>indicatesthelibraryintowhichthesourcespecifiedby<file_name>shouldbecompiled.
TherecanbemultipleVHDLfilenamesperline.
Example:
vhpcomp suba
.
vhd subb
.
vhd
SeevhpcompOverviewandSyntaxformoreinformationaboutthecommand.
GenerationoftheISimSimulationExecutable-Runningfuse
Syntax:
fuse {[<library_name>
.
]<top_name>}
-
o <output_file_name>
where:
{[<library_name>.]<top_name>}isoneormorelibrariesandtopleveldesignunitnames. <library_name>is
optionalandisonlyneededwhenusingadifferentlibrarythanthedefault
work
.Ifspecified,theHDLfile
thatcontainsthetoplevelhastobecompiledintherelatedlibrarynameasreferredintheprojectfile. For
example,designunitnameofthetestbenchfile.
No
t
e
Using
glbl
astop_nameismandatoryifbehavioraldesigninstantiatesUNISIMprimitives.
-
o
switchenablesyoutodefinethesimulationexecutablename(forexample,
my_sim
.
exe
).Without
-
o
,
thedefaultnameforthesimulationexecutableis
x
.
exe
.
Example:
fuse work
.
topunit work
.
glbl
-
o my_sim
.
exe
SeefuseOverviewandSyntaxformoreinformationaboutthefusecommand.
S
i
mu
l
a
t
i
on
AfterthecompilationandtheISimsimulationexecutablegeneration,thefinalstageissimulation. Torunthe
simulation,runtheexecutablefilegeneratedbyfuse.
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Chap
t
er3
:
V
H
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i
mu
l
a
t
i
on
C
ommand
Behav
i
o
r
x
.
exe
(defaultname)oruser-definedexecutable,suchas
my_sim
.
exe
Designissimulated,whencomplete,Tclpromptopensfor
Tclcommandentry.
x
.
exe
-
gui
or
my_sim
.
exe
-
gui
Designissimulated,whencomplete,ISimGUIislaunched.
GUICommandsandTclcommandscanbeusedtoanalyze
design,rerunsimulation,etc.
x
.
exe
-
tclbatch
<
tcl_file_name
>
or
my_sim
.
exe
-
tclbatch
<
tcl_file_name
>
Designissimulated,andTclcommandsspecifiedinTclfile
arerun,withthefinalcommandbeing
quit
command.
SeeISimSimulationExecutableOverviewandSyntaxformoreinformationaboutthecommand.
Runn
i
ngaT
i
m
i
ngS
i
mu
l
a
t
i
on
F
r
om
t
he
C
ommandL
i
neW
i
t
ha
V
H
D
L
D
es
i
gn
G
enera
t
i
ngT
i
m
i
ngS
i
mu
l
a
t
i
onMode
l
Beforelaunchingatimingsimulation,atimingsimulationmodelanddelayfileforback-annotationarerequired.
UsetheNetGentooltogeneratethesefiles. See“GeneratingGate-LevelNetlist(RunningNetGen)”inthe
SynthesisandSimulationDesignGuide.
Me
t
hod1
:
Us
i
ngaP
r
o
j
ec
t
Fil
e-Recommended
CompilationoftheFiles
Createafilecalled
<
proj_name
>.
prj
andusethefollowingsyntaxinsidetheprojectfile:
vhdl
<
library_name
> <
your_testbench
>.
vhd
vhdl
<
library_name
> <
topleve_timesim
>.
vhd
.
vhdl
<
library_name
> <
file_name_n
>.
vhd
<library_name>indicatesthelibrarythatthesourceonthegivenlineshouldbecompiled.Thedefaultlibrary
nameiswork.
<your_testbench>.vhdisthestimulusfile.
<topleve_timesim>.vhdisthetimingsimulationmodelgeneratedbyNetGen(see“GeneratingTiming
SimulationModel”).
<file_name_n>.vhdareanyadditionalsourcefilesrequiredbythetestbench(auxiliarytestbenchfiles,etc.)
GenerationoftheISimSimulationExecutable-Runningfuse
TheHDLlinker,fuse,performsstaticelaborationofadesignintermsofparsednodes,generatesobjectcode
foreachuniquemoduleinstance,andlinksthegeneratedobjectcodeswiththeISimsimulationenginelibrary
tocreateanISimsimulationexecutable.
Syntax:
fuse {[<library_name>
.
]<top_name>}
-
prj <prj_file_name>.prj
-
o <output_file_name>
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3
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Chap
t
er3
:
V
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l
a
t
i
on
where:
{[<library_name>.]<top_name>}isoneormorelibrariesandtopleveldesignunitnames. Thelibraryname
isoptionalandifnotspecifieditisdefaultedto
work
.Ifspecified,theHDLfilethatcontainsthetoplevel
hastobecompiledintherelatedlibrarynameasreferredintheprojectfile. Forexample,designunit
nameofthetestbenchfile.
No
t
e
Using
glbl
astop_nameisnecessary.
-
prj
<proj_file_name>.prjisoptionalinfuseduringtimingsimulation.
-
o
switchisoptional.Without
-
o
,thedefaultnameforthesimulationexecutableis
x
.
exe
.
fuse topunit work
.
glbl
-
prj mydesign
.
prj
-
o my_sim
.
exe
SeefuseOverviewandSyntaxformoreinformationaboutthefusecommand.
Me
t
hod2
:
Us
i
ngvhpcomp
ParsingoftheFiles
Syntax:
vhpcomp [
-
work <library_name>]<file_name>
.
vhd
vhpcomp
-
work <library_name><file_name>
.
vhd
where
-
work
isoptionalandisonlyneededwhentryingtospecifyadifferentlibrarythanthedefault
work
.
<library_name>indicatesthelibraryintowhichthesourcespecifiedby<file_name>shouldbecompiled.
TherecanbemultipleVHDLfilenamesperline.
SeevhpcompOverviewandSyntaxformoreinformationaboutthecommand.
GenerationoftheISimSimulationExecutable-Runningfuse
Syntax:
fuse {[<library_name>.]
<
top_name
>
}
-
o <output_file_name>
where:
{[<library_name>.]<top_name>}isoneormorelibrariesandtopleveldesignunitnames.Forexample,design
unitnameofthetestbenchfile.Includealibrarynameisoptional.Thedefaultnameworkisassumedwhen
librarynameisnotspecified.Examples:
work
.
topunit
,
work
.
glbl
,
mylib
.
glbl
.
-
o
switchisoptional.Without
-
o
,thedefaultnameforthesimulationexecutableis
x
.
exe
.
SeefuseOverviewandSyntaxformoreinformationaboutthefusecommand.
S
i
mu
l
a
t
i
on
AfterthecompilationandISimsimulationexecutablegeneration,thefinalstageissimulation. TheISim
simulationexecutablegeneratedbythefusecommandisruntoeffectsimulation.
IfyouwouldlikeTclcommandscontainedinafiletobeexecutedafterthesimulationhasbegun,usethe
-
tclbatch
switch.
ItisalsopossibletoinstructthesimulatortousethecorrecttimingdelaysfromtheSDFfile.
Syntax:
<executable_name>.exe
-
tclbatch <tcl_file_name>
-
sdfmin|
-
sdftyp|
-
sdfmax
<<anno_point>=sdf_file>.sdf>
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Chap
t
er3
:
V
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i
mu
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on
where
<executable_name>.exeisthesimulationexecutablecalledx.exeunlessotherwisespecifiedwiththe
fuse
-
o
switch.
-
sdfmin|
-
sdftyp|
-
sdfmax
isthetypeofdelay(minimum,typical,ormaximum)thatISimshoulduse.
<anno_point>isthepointofhierarchywhereyouwanttoannotatethedelay.ThisisusuallyUUT.
<sdf_file>isthefilenameoftheSDFfileyouwanttoannotate.
SeeISimSimulationExecutableOverviewandSyntaxformoreinformationaboutthecommand.
L
i
b
raryMapp
i
ng
Fil
e
No
t
e
Thefollowinginformationisintendedforadvancedusers.
TheISimHDLcompileprograms,vhpcomp,vlogcompandfuse,usethe
xilinxsim
.
ini
configurationfileto
learnthedefinitionsandphysicallocationsofVHDLandVeriloglogicallibraries.
SearchO
r
der
Thecompilersattempttoread
xilinxsim
.
ini
fromtheselocationsinthefollowingorder.
1.
$
X
ILIN
X
/
vhdl
/
hdp
/<
platform
>
.
2. Userfilespecifiedthroughthe
-
initfile
switchin
vlogcomp
,
vhpcomp
or
fuse
.If
-
initfile
isnot
specified,"
xilinxsim
.
ini
"inthecurrentworkingdirectoryissearchedfor.
Syn
t
ax
The
xilinxsim
.
ini
filehasthefollowingformat:
<
logical_library
1> = = <
physical_dir_path
1>
<
logical_library
2> = = <
physical_dir_path
2>
.
.
<
logical_libraryn
> = = <
physical_dir_pathn
>
Examp
l
e
Thefollowingisanexampleofa
xilinxsim
.
ini
file:
VHDL
std
=C:/
libs
/
vhdl
/
hdp
/
stdieee
=C:/
libs
/
vhdl
/
hdp
/
ieee
work
=C:/
work
Verilog
unisims_ver
=$
X
ILIN
X
/
rtf
/
verilog
/
hdp
/
nt
/
unisims_ver
xilinxcorelib_ver
=C:/
libs
/
verilog
/
hdp
/
nt
/
xilinxcorelib_ver
mylib
=./
mylib
work
=C:/
work
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C# PDF File & Page Process Library SDK for C#.net, ASP.NET, MVC
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Chap
t
er3
:
V
H
D
L S
i
mu
l
a
t
i
on
F
ea
t
u
res/L
i
m
i
t
a
t
i
ons
The
xilinxsim
.
ini
filehasthefollowingfeaturesandlimitations:
Theremustbenomorethanonelibrary/pathperlinespecifiedinsidethe
xilinxsim
.
ini
file.
Ifthedirectorycorrespondingtothephysicalpathdoesnotexist,
vhpcomp
or
vlogcomp
createsitwhenthe
compilerfirsttriestowritetoit.
Youcandescribethephysicalpathintermsofenvironmentvariables. Theenvironmentvariablemust
startwith$character.
Thedefaultphysicaldirectoryforalogicallibraryis
isim
/<
logical_library_name
>
.
Allcommentsinthisfilemuststartwith’--’.
I
n
t
erac
t
i
veS
i
mu
l
a
t
i
on
i
n
C
ommandL
i
neMode
Whenasimulationisrunincommandlinemode,aTclpromptopensandyoucanentersimulationTcl
commands,whichenableyoutorunsimulation,analyzethedesign,anddebugthedesign.Formoreinformation
aboutSimulationCommands,seeSimulationCommandOverview. Fortipsonhowtoentercommands,see
EnteringSimulationTclCommands.
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Chapter4
VerilogSimulation
Ver
il
ogS
i
mu
l
a
t
i
onOverv
i
ew
Runningasimulationfromthecommandlineinvolvesthreebasicsteps:
1. Parsingthedesignfiles
2. GeneratingtheISimsimulationexecutable
3. Simulatingthedesign
Gototheappropriatesimulationtopicfordetails:
RunningaFunctionalSimulationattheCommandLine
RunningaTimingSimulationattheCommandLine
Runn
i
nga
F
unc
t
i
ona
l
S
i
mu
l
a
t
i
ono
f
aVer
il
og
D
es
i
gn
F
r
om
t
he
C
ommandL
i
ne
Inafunctional(behavioral)simulationofaVerilogdesign,thestepsmustbefollowedifUNISIMprimitivesare
used:
Compile
$
X
ILIN
X
/
Verilog
/
src
/
glbl
.
v
tolibrary
work
.
Specify
work
.
glbl
asoneofthe<library_name>.<top_name>in
fuse
.
Specify
-L
unisims_ver
in
fuse
.
Me
t
hod1
:
Us
i
ngaP
r
o
j
ec
t
Fil
e-Recommended
ParsingtheDesignFiles
Createafilecalled
<
proj_name
>.
prj
andusethefollowingsyntaxinsidetheprojectfile:
verilog
<
library_name
>
{
<
file_name_
1>.
v} {[
-
d
<
macro
>
] [
-
i
<
include_path
>
]}
verilog
<
library_name
>
{
<
file_name_
2>.
v} {[
-
d
<
macro
>
] [
-
i
<
include_path
>
]}
.
verilog
<
library_name
>
{
<
file_name_n
>.
v} {[
-
d
<
macro
>
] [
-
i
<
include_path
>
]}
where:
verilogindicatesthatthesourceisaVerilogfile.
<library_name>indicatesthelibraryintowhichthesourceonthegivenlineshouldbecompiled. Morethan
oneVerilogsourcecanbespecifiedonagivenline.
[-d<macro>]definesoneormoremacrolocatedinthelocationspecifiedin[-i<include_path>].
Example:
verilog work top
.
v testbench
.
v
GeneratingtheISimSimulationExecutable-Runningfuse
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7
Chap
t
er 4
:
Ver
il
og S
i
mu
l
a
t
i
on
TheHDLlinker,fuse,performsstaticelaborationofadesignintermsofparsednodes,generatesobjectcode
foreachuniquemoduleinstance,andlinksthegeneratedobjectcodeswiththeISimsimulationenginelibrary
tocreateanISimsimulationexecutable.
Syntax:
fuse {[<library_name>
.
]<top_name>}
-
prj <prj_file_name>.prj
-L
<Verilog_library>
-
o <output_file_name>
where:
{[<library_name>.]<top_name>}isoneormorelibrariesandtopleveldesignunitnames. Thelibraryname
isoptionalandifnotspecifieditisdefaultedto
work
.Ifspecified,theHDLfilethatcontainsthetoplevel
hastobecompiledintherelatedlibrarynameasreferredintheprojectfile. Forexample,designunit
nameofthetestbenchfile.
No
t
e
Using
glbl
astop_nameismandatoryifbehavioraldesigninstantiatesUNISIMprimitives.
-L
<Verilog_library>mustinclude
unisims_ver
ifbehavioralsimulationreliesonUNISIMprimitives,in
additiontootherXilinxlibrariesthatapplytothedesign,suchas
unimacro_ver
and
xilinxcorelib_ver
.
-
o
switchisoptional.Without
-
o
,thedefaultnameforthesimulationexecutableis
x
.
exe
.
Example:
fuse work
.
test_bench work
.
glbl
-
prj mydesign
.
prj
-L
unisims_ver
-L
unimacro_ver
-L
xilinxcorelib_ver
-
o test_bench
.
exe
SeefuseOverviewandSyntaxformoreinformationaboutthefusecommand.
Me
t
hod2
:
Pars
i
ng
t
he
Fil
esUs
i
ngv
l
ogcomp
ParsingtheDesignFiles
Syntax:
vlogcomp [
-
work <library_name>] <file_name>
.
v {[
-
d
<
macro
>
] [
-
i
<
include_path
>
]
where
-
work
isoptionalandisonlyneededwhentryingtospecifyadifferentlibrarythanthedefault
work
.
<library_name>indicatesthelibraryintowhichthesourcespecifiedby<file_name>shouldbecompiled.More
thanoneVerilogsourcecanbespecifiedonagivenline.
-
d
<macro>definesoneormoremacrolocatedinthelocationspecifiedin-i<include_path>.
Example:
vlogcomp suba
.
v subb
.
v
SeevlogcompOverviewandSyntaxformoreinformationaboutthevlogcompcommand.
GenerationoftheISimSimulationExecutable-Runningfuse
Syntax:
fuse {[<library_name>
.
]<top_name>} {
-L
<Verilog_library>}
-
o <output_file_name>
where:
{[<library_name>.]<top_name>}isoneormoretoplevelofdesignunitnamescanbespecified.Forexample,
designunitnameofthetestbenchfile.Onetopnamemustbe
glbl
. Includingalibrarynameisoptional.
Thedefaultlibraryname
work
isassumedwhenalibrarynameisnotspecified.
No
t
e
Formoreinformationabouttheglobalmodule,see“GlobalSet/Reset(GSR)andGlobalTristate(GTS)
inVerilog”intheSynthesisandSimulationDesignGuide.
-L
<Verilog_library>mustinclude
unisim
inadditiontootherXilinxlibrariesthatapplytothedesign,
suchas
unimacro
and
xilinxcorelib
.
-
o
switchisoptional.Without
-
o
,thedefaultnameforthesimulationexecutableis
x
.
exe
.
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ogS
i
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a
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i
on
Example:
fuse work
.
test_bench work
.
glbl
-L
unisims_ver
-L
unimacro_ver
-L
xilinxcorelib_ver
-
o test_bench
.
exe
SeefuseOverviewandSyntaxformoreinformationaboutthefusecommand.
S
i
mu
l
a
t
i
on
AfterthecompilationandtheISimsimulationexecutablegeneration,thefinalstageissimulation. Torunthe
simulation,runtheexecutablefilegeneratedbyfuse.
C
ommand
Behav
i
o
r
x
.
exe
(defaultname)oruser-definedexecutable,suchas
my_sim
.
exe
Designissimulated,whencomplete,Tclpromptopensfor
Tclcommandentry.
x
.
exe
-
gui
or
my_sim
.
exe
-
gui
Designissimulated,whencomplete,ISimGUIislaunched.
GUICommandsandTclcommandscanbeusedtoanalyze
design,rerunsimulation,etc.
x
.
exe
-
tclbatch
<
tcl_file_name
>
or
my_sim
.
exe
-
tclbatch
<
tcl_file_name
>
Designissimulated,andTclcommandsspecifiedinTclfile
arerun,withthefinalcommandbeing
quit
command.
SeeISimSimulationExecutableOverviewandSyntaxformoreinformationaboutthecommand.
Runn
i
ngaT
i
m
i
ngS
i
mu
l
a
t
i
ono
f
aVer
il
og
D
es
i
gn
F
r
om
t
he
C
ommandL
i
ne
InatimingsimulationofaVerilogdesign,thefollowingrulesmustbefollowed:
Compile
$
X
ILIN
X
/
Verilog
/
src
/
glbl
.
v
tolibrary
work
.
Specify
work
.
glbl
asoneofthe<library_name>.<top_name>in
fuse
.
Specify
-L
simprims_ver
in
fuse
.
G
enera
t
i
ngT
i
m
i
ngS
i
mu
l
a
t
i
onMode
l
Beforelaunchingatimingsimulation,atimingsimulationmodelanddelayfileforback-annotationarerequired.
UsetheNetGentooltogeneratethesefiles. See“GeneratingGate-LevelNetlist(RunningNetGen)”inthe
SynthesisandSimulationDesignGuide.
Me
t
hod1
:
Us
i
ngaP
r
o
j
ec
t
Fil
e-Recommended
CompilationoftheFiles
Createafilecalled
<
proj_name
>.
prj
andusethefollowingsyntaxinsidetheprojectfile:
verilog
<
library_name
>
{
<
file_name
>.
v} {[
-
d
<
macro
>
] [
-
i
<
include_path
>
]}
where
verilogindicatesthatthesourceisaVerilogfile.MorethanoneVerilogsourcecanbespecifiedonagivenline.
<library_name>isthetargetlibraryintowhichthesource(s)onthatparticularlineshouldbecompiled.
[-d<macro>]allowsyoutodefineoneormoremacroofthepathspecifiedby[-i<include_path>]. These
optionsareoptional.
Example1:
verilog work top
.
v testbench
.
v
verilog work glbl
.
v
verilog work top_timesim
.
v
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Chap
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:
Ver
il
og S
i
mu
l
a
t
i
on
GenerationoftheISimSimulationExecutable-Runningfuse
TheHDLlinker,fuse,performsstaticelaborationofadesignintermsofparsednodes,generatesobjectcode
foreachuniquemoduleinstance,andlinksthegeneratedobjectcodeswiththeISimsimulationenginelibrary
tocreateanISimsimulationexecutable.
Syntax:
fuse {[<library_name>.]<top_name>}
-
prj <prj_file_name>.prj j {
-L
<verilog_library_name> }
-
o <output_file_name>
where:
{[<library_name>.]<top_name>}isoneormoretoplevelofdesignunitnamescanbespecified.Forexample,
designunitnameofthetestbenchfile.Onetopnamemustbe
glbl
. Includingalibrarynameisoptional.
Thedefaultlibraryname
work
isassumedwhenalibrarynameisnotspecified.
-L
<Verilog_library>mustinclude
simsprims_ver
inadditiontootherXilinxlibrariesthatapplytothe
design.
-
o
switchisoptional.Without
-
o
,thedefaultnameforthesimulationexecutableis
x
.
exe
.
Example:
fuse work
.
testbench work
.
glbl
-
prj design
.
prj
-L
simprims_ver
-
o isim
.
exe
SeefuseOverviewandSyntaxformoreinformationaboutthefusecommand.
Me
t
hod2
:
Pars
i
ng
t
he
Fil
esUs
i
ngv
l
ogcomp
ParsingtheFiles
Syntax:
vlogcomp [
-
work <library_name>]<file_name>.v
where
-
work
isoptionalandisonlyneededwhentryingtospecifyadifferentlibrarythanthedefault
work
.
<library_name>indicatesthelibraryintowhichthesourcespecifiedby<file_name>shouldbecompiled.More
thanoneVerilogsourcecanbespecifiedonagivenline.
Example:
vlogcomp top_testbench
.
v top_timesim
.
v
SeevlogcompOverviewandSyntaxformoreinformationaboutthevlogcompcommand.
GenerationoftheISimSimulationExecutable-Runningfuse
Syntax:
fuse {[<library_name>.]<top_name>} {
-L
<Verilog_library>}
-
o <output_file_name>
where:
{[<library_name>.]<top_name>}isoneormoretoplevelofdesignunitnamescanbespecified.Forexample,
designunitnameofthetestbenchfile.Onetopnamemustbe
glbl
. Includingalibrarynameisoptional.
Thedefaultlibraryname
work
isassumedwhenalibrarynameisnotspecified.
-L
<Verilog_library>mustinclude
simsprims_ver
inadditiontootherXilinxlibrariesthatapplytothe
design.
-
o
switchisoptional.Without
-
o
,thedefaultnameforthesimulationexecutableis
x
.
exe
.
Example:
fuse work
.
textbench work
.
glbl
-L
simprims_ver
-
o timesim
.
exe
SeefuseOverviewandSyntaxformoreinformationaboutthefusecommand.
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50
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ili
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G
660(v11.
3
)
Sep
t
ember16,2
00
9
Documents you may be interested
Documents you may be interested