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Chap
t
er4
:
Ver
il
ogS
i
mu
l
a
t
i
on
S
i
mu
l
a
t
i
on
AfterthecompilationandISimsimulationexecutablegeneration,thefinalstageissimulation. TheISim
simulationexecutablegeneratedbythefusecommandisruntoeffectsimulation.
IfyouwouldlikeTclcommandscontainedinafiletobeexecutedafterthesimulationhasbegun,usethe
-
tclbatch
switch.
ItisalsopossibletoinstructthesimulatortousethecorrecttimingdelaysfromtheSDFfile.
Syntax:
<executable_name>.exe
-
tclbatch <tcl_file_name>
-
sdfmin|
-
sdftyp|
-
sdfmax
<<anno_point>=sdf_file>.sdf>
where
<executable_name>.exeisthesimulationexecutablecalledx.exeunlessotherwisespecifiedwiththe
fuse
-
o
switch.
-
sdfmin|
-
sdftyp|
-
sdfmax
isthetypeofdelay(minimum,typical,ormaximum)thatISimshoulduse.
<anno_point>isthepointofhierarchywhereyouwanttoannotatethedelay.ThisisusuallyUUT.
<sdf_file>isthefilenameoftheSDFfileyouwanttoannotate.
SeeISimSimulationExecutableOverviewandSyntaxformoreinformationaboutthecommand.
SearchO
r
derf
o
r
I
ns
t
anceo
f
Ver
il
og
D
es
i
gnUn
i
t
s
TheHDLlinker,fuse,usesthefollowingsearchorderinordertosearchandbindinstantiatedVerilogDesign
Unitsinadesign.
1. Libraryspecifiedby‘uselibdirective.
2. Librariesspecifiedonthecommandlinewith
-
lib
|
-L
switch.
3. Libraryoftheparentdesignunit.
4. Logicalworklibrary.
Suppo
rt
i
ngSou
rceL
i
b
rar
i
es
ThecompilerargumentslistedbelowsupportsourcelibrariesinthesamemannerasVerilog-XL.Seethe
vlogcompOptionsorthefuseOptionsforadescriptionofeachargument.
Inordertousethisfeature,thefollowingcommandoptionswillneedtobepassedtothevlogcompVerilog
compiler.
L
i
b
raryLoca
t
i
on(-sou
rce
li
bd
i
r)
No
t
e
-sourcelibdirprovidesfunctionalitythatissimilartothe-yswitchinVerilog-XL.
Afterthesourcefilesonthecommandlinehavebeencompiled,ifthereareanyunresolvedreferencesto
modules,thecompilersearchesthesourcelibrariesforresolution.Duringthissearch,thecompilerattempts
tomatchthenameofanyunresolvedinstantiateddesignunitwithafileofthesamenameinthespecified
-sourcelibdirdirectory.Ifsuchafileexists,compileranalyzesthatfile.Alsonotethatbydefaultthecompiler
ignoresanyfileswithextensionssuchas.v,.h,etc,unless-sourcelibextisalsoused.
-
sourcelibdir
<
library_first
> -
sourcelibdir
<
library_second
>
Sou
rce
Fil
eEx
t
ens
i
on(-sou
rce
li
bex
t)
No
t
e
-sourcelibextprovidesfunctionalitythatissimilartothe+libext+switchinVerilog-XL.
Thiscommandlineargumentmaybeusedinconjunctionwith-sourcelibdirwhenthesourcelibraryfiles
haveextensions.
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Add photo to pdf form - insert images into PDF in C#.net, ASP.NET, MVC, Ajax, WinForms, WPF
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Chap
t
er 4
:
Ver
il
og S
i
mu
l
a
t
i
on
-
sourcelibext
.
v
Sou
rce
Fil
e(-sou
rce
li
b
fil
e)
No
t
e
-sourcelibfileprovidesfunctionalitysimilartothe-vswitchinVerilog-XL.
ISimalsoenablesyoutoprovideasourceVeriloglibraryfilethatcontainsdefinitionsofalltheunresolved
modules.
-
sourcelibfile
./
library
/
lib_abc
.
v
Examp
l
es
Thefollowingexamplesdemonstratetheuseofthesecommandoptions.
Vlogcomp
vlogcomp
-
work mywork
1
file
1.
v
-
sourcelibdir mydir
/
cells
Thecompilersearchesforunresolvedcellsinsidedirectory
mydir
/
cells
.Forexample,if
file
1.
v
instantiates
DFFandDMUX,whichareunresolved,thenthecompilerwouldlookforfileswithnamesDFFandDMUX
insidedirectory
mydir
/
cells
.FilesDFFandDMUXshoulddefinemodulesDFFandDMUX.
Fuse
fuse
prj test
.
prj test
-
sourcelibfile
./
mylib
1/
lib_abc
.
v
-
sourcelibfile
./
mylib
1/
lib_cde
.
v
where
test
.
prj
contains:
verilog work test
.
v
Thecompilerusesfilesgivenbythe-sourcelibfileoptionsformodulesusedin
test
.
v
.Itanalyzesthemodules
andelaboratesthe
test
design
ProjectFile
fuse
prj test
.
prj test
where
test
.
prj
contains:
verilog work test
.
v
-
sourcelibdir
./
mylib
1 –
sourcelibdir
./
mylib
2 -
sourcelibext
.
v
Foreveryunresolvedmodulewithnamemodulenameinstantiatedinfile
test
.
v
,thecompilerlooksupfileswith
name
modulename
.
v
insidethedirectories
./
mylib
1
and
./
mylib
2
,inthatorder.
L
i
b
raryMapp
i
ng
Fil
e
No
t
e
Thefollowinginformationisintendedforadvancedusers.
TheISimHDLcompileprograms,vhpcomp,vlogcompandfuse,usethe
xilinxsim
.
ini
configurationfileto
learnthedefinitionsandphysicallocationsofVHDLandVeriloglogicallibraries.
SearchO
r
der
Thecompilersattempttoread
xilinxsim
.
ini
fromtheselocationsinthefollowingorder.
1.
$
X
ILIN
X
/
vhdl
/
hdp
/<
platform
>
.
2. Userfilespecifiedthroughthe
-
initfile
switchin
vlogcomp
,
vhpcomp
or
fuse
.If
-
initfile
isnot
specified,"
xilinxsim
.
ini
"inthecurrentworkingdirectoryissearchedfor.
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VB.NET Image: Mark Photo, Image & Document with Polygon Annotation
on PDF file without using external PDF editing software. VB.NET Methods to Add Polygon Annotation. In this Public Partial Class Form1 Inherits Form Public Sub
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Chap
t
er4
:
Ver
il
ogS
i
mu
l
a
t
i
on
Syn
t
ax
The
xilinxsim
.
ini
filehasthefollowingformat:
<
logical_library
1> = = <
physical_dir_path
1>
<
logical_library
2> = = <
physical_dir_path
2>
.
.
<
logical_libraryn
> = = <
physical_dir_pathn
>
Examp
l
e
Thefollowingisanexampleofa
xilinxsim
.
ini
file:
VHDL
std
=C:/
libs
/
vhdl
/
hdp
/
stdieee
=C:/
libs
/
vhdl
/
hdp
/
ieee
work
=C:/
work
Verilog
unisims_ver
=$
X
ILIN
X
/
rtf
/
verilog
/
hdp
/
nt
/
unisims_ver
xilinxcorelib_ver
=C:/
libs
/
verilog
/
hdp
/
nt
/
xilinxcorelib_ver
mylib
=./
mylib
work
=C:/
work
F
ea
t
u
res/L
i
m
i
t
a
t
i
ons
The
xilinxsim
.
ini
filehasthefollowingfeaturesandlimitations:
Theremustbenomorethanonelibrary/pathperlinespecifiedinsidethe
xilinxsim
.
ini
file.
Ifthedirectorycorrespondingtothephysicalpathdoesnotexist,
vhpcomp
or
vlogcomp
createsitwhenthe
compilerfirsttriestowritetoit.
Youcandescribethephysicalpathintermsofenvironmentvariables. Theenvironmentvariablemust
startwith$character.
Thedefaultphysicaldirectoryforalogicallibraryis
isim
/<
logical_library_name
>
.
Allcommentsinthisfilemuststartwith’--’.
P
rede
nedX
I
L
I
NX_S
I
MMacr
o
f
o
r
Ver
il
ogS
i
mu
l
a
t
i
on
XILINX_ISIMisaVerilogpredefinedmacrospecifictoISim,andthevalueofthismacrois’1’.Thesepredefined
macrosareusedtoperformtoolspecificfunctionsorsometimesjusttoidentifywhichtooltouseinadesignflow.
module
isim_predefined_macro
;
integer fp
;
initial
begin
ifdef X
ILIN
X_
ISIM
$
display
("
X
ILIN
X_
ISIM
defined
");
fp
= $
fopen
("ISIM.
dat
");
else
$
display
("
X
ILIN
X_
ISIM
not defined
");
fp
= $
fopen
("
other
.
dat
");
endif
$
fdisplay
(
fp
, "
results
");
end
endmodule
I
n
t
erac
t
i
veS
i
mu
l
a
t
i
on
i
n
C
ommandL
i
neMode
Whenasimulationisrunincommandlinemode,aTclpromptopensandyoucanentersimulationTcl
commands,whichenableyoutorunsimulation,analyzethedesign,anddebugthedesign.Formoreinformation
aboutSimulationCommands,seeSimulationCommandOverview. Fortipsonhowtoentercommands,see
EnteringSimulationTclCommands.
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3
VB.NET Image: Image Scaling SDK to Scale Picture / Photo
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VB.NET Image: How to Save Image & Print Image Using VB.NET
of saving and printing multi-page document files, like PDF and Word printing assembly with VB.NET web image viewer add-on, you VB.NET Code to Save Image / Photo.
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C# Image: How to Add Antique & Vintage Effect to Image, Photo
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Chapter5
MixedLanguageSimulation
M
i
xedLanguageS
i
mu
l
a
t
i
onOverv
i
ew
No
t
e
Thefollowinginformationisintendedforadvancedusers.
ISimsupportsmixedlanguageprojectfilesandmixedlanguagesimulation.ThisenablesyoutoincludeVerilog
modulesinaVHDLdesign,andviceversa. Somerestrictionsdoapply:
Res
tr
i
c
t
i
onsonM
i
xedLanguage
i
nS
i
mu
l
a
t
i
on
MixingVHDLandVerilogisrestrictedtothemoduleinstanceorcomponentonly. AVHDLdesigncan
instantiateVerilogmodulesandaVerilogdesigncaninstantiateVHDLcomponents.Anyothermixuse
ofVHDLandVerilogisnotsupported.
AVeriloghierarchicalreferencecannotrefertoaVHDLunitnorcanaVHDLexpanded/selectedname
refertoaVerilogunit.
OnlyasmallsubsetofVHDLtypes,genericsandportsareallowedontheboundarytoaVerilogmodule.
Similarly,asmallsubsetofVerilogtypes,parametersandportsareallowedontheboundarytoVHDL
designunit.
Componentinstantiation-baseddefaultbindingisusedforbindingaVerilogmoduletoaVHDLdesignunit.
Specifically,configurationspecification,directinstantiationandcomponentconfigurationsarenotsupported
foraVerilogmoduleinstantiatedinsideaVHDLdesignunit.
KeyS
t
eps
i
naM
i
xedLanguageS
i
mu
l
a
t
i
on
Instantiatemixedlanguagecomponents. SeeInstantiatingaVerilogModuleinaVHDLDesignUnitor
InstantiatingaVHDLModuleinaVerilogDesignUnit
Optionally,specifythesearchorderforVHDLentityorVerilogmodulesinthedesignlibrariesofamixed
languageproject.
Usethe
fuse
-L
optiontospecifythebindingorderofaVHDLentityoraVerilogmoduleinthedesign
librariesofamixedlanguageproject. Notethatthelibrarysearchorderspecifiedby
-L
isusedforbinding
VerilogmodulestootherVerilogmodulesaswell.
Runthesimulation.
I
ns
t
an
t
i
a
t
i
ngM
i
xedLanguage
C
omponen
t
s
I
ns
t
an
t
i
a
t
i
ngaVer
il
ogModu
l
e
i
naV
H
D
L
D
es
i
gnUn
i
t
Inamixedlanguagedesign,youcaninstantiateaVerilogmoduleinaVHDLdesignunit.
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VB.NET Image: Tutorial for Flipping Image Using Our .NET Image SDK
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C# PDF remove image library: remove, delete images from PDF in C#.
Highlight Text. Add Text. Add Text Box. Drawing vector image, graphic picture, digital photo, scanned signature and remove multiple or all images from PDF document
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Chap
t
er5
:
M
i
xedLanguageS
i
mu
l
a
t
i
on
To
I
ns
t
an
t
i
a
t
eaVer
il
ogModu
l
e
i
naV
H
D
L
D
es
i
gnUn
i
t
1. DeclareaVHDLcomponentwiththesamenameastheVerilogmodule(respectingcasesensitivity)
thatyouwanttoinstantiate.
Forexample,
COMPONENT M
Y_V
HDL
_
UNIT PORT (
Q :
out
STD
_
ULOGIC;
D :
in
STD
_
ULOGIC;
C :
in
STD
_
ULOGIC );
END COMPONENT;
2. UsenamedassociationtoinstantiatetheVerilogmodule.
Forexample,
UUT : : M
Y_V
HDL
_
UNIT PORT T MAP(
Q => O,
D => I,
C => CLK);
Toensurethatyouarecorrectlymatchingporttypes,seeportmappingrulesinMixedLanguageBoundary
andMappingRules.
SinceVerilogiscasesensitive,namedassociationsandthelocalportnamesthatyouuseinthecomponent
declarationmustmatchthecaseofthecorrespondingVerilogportnames.
I
ns
t
an
t
i
a
t
i
ngaV
H
D
LModu
l
e
i
naVer
il
og
D
es
i
gnUn
i
t
Inamixedlanguagedesign,youcaninstantiateaVHDLmoduleinaVerilogdesignunit.
To
I
ns
t
an
t
i
a
t
eaV
H
D
LModu
l
e
i
naVer
il
og
D
es
i
gnUn
i
t
InstantiatetheVHDLentityasifitwereaVerilogmodule.
Forexample,
module testbench
;
wire in
,
clk
;
wire out
;
FD FD1(
.Q(Q
_
OUT),
.C(CLK);
.D(A);
);
M
i
xedLanguageB
i
nd
i
ngandSearch
i
ng
No
t
e
Thefollowinginformationisintendedforadvancedusers.
WhenyouinstantiateaVHDLcomponentoraVerilogmodule,thefuselinkerfirstsearchesforaunitofthesame
languageasthatoftheinstantiatingdesignunit.Ifaunitofthesamelanguageisnotfound,fusesearchesfora
crosslanguagedesignunitinthelibrariesspecifiedinthe
-
lib
option. Thesearchorderisthesameasthe
orderofappearanceoflibrariesonfusecommandline.FormoreinformationaboutVeriloglibrarysearchorder,
seeSearchOrderforInstanceofVerilogDesignUnits.
No
t
e
WhenusingtheISE®software,thelibrarysearchorderisspecifiedautomatically. Nouserintervention
isnecessaryorpossible.
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Chap
t
er5
:
M
i
xedLanguageS
i
mu
l
a
t
i
on
V
H
D
L
I
ns
t
an
t
i
a
t
i
onUn
i
t
WhenaVHDLdesigninstantiatesacomponent,thefuselinkertreatsthecomponentnameasaVHDLunit
andsearchesforitinlogicallibrary"work". IfaVHDLunitisfound,fusebindsitandthesearchstops. If
fusecannotfindaVHDLunit,ittreatsthecasepreservedcomponentnameasaVerilogmodulenameand
continuestosearchasfollows:
PerformsacasesensitivesearchforaVerilogmoduleintheuserspecifiedlistofunifiedlogicallibrariesin
theuserspecifiedsearchorder.Thefirstonematchingthenameispickedandthesearchstops.
Ifcasesensitivesearchisnotsuccessful,performsacaseinsensitivesearchforaVerilogmoduleintheuser
specifiedlistofunifiedlogicallibrariesintheuserspecifiedsearchorder.Ifauniquebindingisfoundforany
onelibrary,thesearchstops.
Ver
il
og
I
ns
t
an
t
i
a
t
i
onUn
i
t
WhenaVerilogdesigninstantiatesacomponent,thefuselinkertreatsthecomponentnameasaVerilogunitand
searchesforaVerilogmoduleintheuserspecifiedlistofunifiedlogicallibrariesintheuserspecifiedorder.If
found,fusebindsitandthesearchstops.IffusecannotfindaVerilogunit,ittreatsthenameoftheinstantiated
moduleasaVHDLentitynameandcontinuesthesearchasfollows:
Performsacaseinsensitivesearchforanentitywiththesamenameastheinstantiatedmodulenameinthe
userspecifiedlistofunifiedlogicallibrariesintheuserspecifiedorder.Thefirstonematchingthenameis
pickedandthesearchstops.
PerformsacasesensitivesearchforaVHDLdesignunitnameconstructedasanextendedidentifierinthe
userspecifiedlistofunifiedlogicallibrariesintheuserspecifiedorder.Ifauniquebindingisfoundforany
onelibrary,thenameispickedandthesearchstops.
No
t
e
Foramixedlanguagedesign,theportnamesusedinanamedassociationtoaVHDLentityinstantiatedby
aVerilogmodulearealwaystreatedascaseinsensitive.Alsonotethatyoucannotuseadefparamstatementto
modifyaVHDLgeneric.
M
i
xedLanguageBoundaryandMapp
i
ngRu
l
es
No
t
e
Thefollowinginformationisintendedforadvancedusers.
G
enera
l
ThefollowingrestrictionsapplytotheboundariesbetweenVHDLandVerilogdesignunits/modules.
TheboundarybetweenVHDLandVerilogisenforcedatdesignunitlevel.
AVHDLdesignisallowedtoinstantiateoneormoreVerilogmodules.
InstantiationofaVerilogUDPinsideaVHDLdesignisnotsupported.
AVerilogdesigncaninstantiateaVHDLcomponentcorrespondingtoaVHDLentityonly.Instantiationofa
VHDLconfigurationinaVerilogdesignisnotsupported.
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7
Chap
t
er5
:
M
i
xedLanguageS
i
mu
l
a
t
i
on
Po
rt
Mapp
i
ng
Thefollowingrulesandlimitationsforportmappingareusedinmixedlanguageprojects.
SupportedVHDLporttypes:
IN
OUT
INOUT
No
t
e
BufferandlinkageportsofVHDLarenotsupported.
SupportedVerilogporttypes:
INPUT
OUTPUT
INOUT
No
t
e
Connectiontobi-directionalpassswitchesinVerilogarenotsupported.
UnnamedVerilogportsarenotallowedonmixeddesignboundary.
ThefollowingtableshowssupportedVHDLandVerilogdatatypesforportsonthemixedlanguagedesign
boundary:
V
H
D
LPo
rt
Ver
il
ogPo
rt
bit
net
std_ulogic
net
std_logic
net
bit_vector
vectornet
std_ulogic_vector
vectornet
std_logic_vector
vectornet
No
t
e
Verilogoutputportoftyperegissupportedonthemixedlanguageboundary.Ontheboundary,anoutput
regportistreatedasifitwereanoutputnet(wire)port.
No
t
e
Anyothertypefoundonmixedlanguageboundaryisconsideredanerror.
G
ener
i
cs(
Parame
t
ers)
Mapp
i
ng
FollowingVHDLgenerictypes(andtheirVerilogequivalents)aresupported.
integer
real
string
boolean
No
t
e
Anyothergenerictypefoundonmixedlanguageboundaryisconsideredanerror.
V
H
D
L/Ver
il
ogVa
l
uesMapp
i
ng
Verilogstatesaremappedtostd_logicandbitasshowninthefollowingtable.
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Chap
t
er5
:
M
i
xedLanguageS
i
mu
l
a
t
i
on
Ver
il
og
s
t
d_
l
og
i
c
b
i
t
Z
’Z’
’0’
0
’0’
’0’
1
’1’
’1’
X
’X’
’0’
No
t
e
Verilogstrengthisignored.ThereisnocorrespondingmappingtostrengthinVHDL.
VHDLtypebitismappedtoVerilogstatesinthefollowingtable.
b
i
t
Ver
il
og
’0’
0
’1’
1
VHDLtypestd_logicismappedtoVerilogstatesinthefollowingtable.
s
t
d_
l
og
i
c
Ver
il
og
’U’
X
’X’
X
’0’
0
’1’
1
’Z’
Z
’W’
X
’L’
0
’H’
1
’-’
X
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