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Spectrum of NRZ data
a
variations due to DC balance strategy
1⁄2T
1⁄T
3⁄2T
2⁄T
f
= 0
2pfT
(
)
sin
2pfT
-------------------------
missing clock
frequency
p
o
w
e
r
i
n
d
B
20
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NRZ and RZ signalling
NRZ = “non return to zero” data
RZ = “return to zero” data
+
+
+
+
+
+
+
+
+
+
n
e
i
t
h
e
r
clock
n
o
r
data frequency in
spectrum
c
l
o
c
k
,but
n
o
data
frequency in
spectrum
data frequency
clock frequency
T
NRZ signalling is almost universally used.
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Filter Method Examples
ddt
X
2
bandpass
filter
bandpass
filter
delay
N
R
Z
D
a
t
a
I
n
p
u
t
R
e
c
o
v
e
r
e
d
C
l
o
c
k
O
u
t
p
u
t
e.g.: SAW filter
LC tank
non-linear element
(this last circuit can be thought of as an NRZ-RZ converter)
[Yam80][YTY80]
[RFC84][Ros84]
[FHH84][AFK87]
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Summary of Filter Method
Retimed Data
Jittered NRZ Data Signal
ddt
X
2
bandpass
filter/limiter
D Q
Con:
Temperatureandfrequencyvariation
of filter group delay makes sampling
time difficult to control
Narrow pulses imply high f
T
Hi-Q filter difficult to integrate
Pro:
Very simple to implement
Can be built with
microwave “tinkertoys”
using coax to very high
frequencies
t
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Phase
Detector
Low-pass
Loop Filter
Voltage
Controlled
Oscillator
D
Retimed
Data
JitteredData
Signal
PLL
Q
25
Data Recovery with simple PLL
e PLL
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x( )t
A
cosw
c
t
=
x()t
A
w
c
f ( )t
+
[
]
cos
=
Perfect Clock:
Jittered Clock:
is then treated as a continuous time signal
f( t)
After Behzad Razavi: “Monolithic Phase-Locked Loops, ISSCC96 Tutorial”
26
Analytic Treatment of Jitter
Jitter
r
Phase
Detector
Loop
Filter
VCO
K
f
1
s
---
K
v
b
1
(1+st
)
-------------------
+
Warning: Extra Integration in loop makes for tricky design!
27
See Floyd M. Gardner, “Phaselock Techniques”, John Wiley and Sons, for good introduction to PLL theory
Model of Loop
Loop
p
28
K
v
s
------
K
f
b
1
(1+st
)
-------------------
+
a
b
c
c/a
c/b
open loop gain
10k
100k
1M
10M
100M
1G
10G
1k
0dB
40dB
80dB
-40dB
-80dB
(input
data jitter)
Loop frequency response
Phase Detectors
PhasedetectorsgenerateaDCcomponentproportional
to deviation of the sampling point from center of bit-cell
Phase detectors are:
Binaryquantizedphasedetectorsarealsocalled“Bang-
bang” phase detectors
90°
180°
–90 °
–180
°
Continuous
Binary Quantized
After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”, (see bibliography for full citation)
29
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