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[Hog85][Shi87]
D Q
D Q
UP
DOWN
Data
Clock
Data
1 = Data.................
2= Clock (Early).....
3 = 1 retimed..........
4 = Clock.................
5 = 3 retimed..........
6 = 1 xor 3 (UP).....
7 = 3xor 5 (DOWN)
“Self-Correcting Phase Detector”
30
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Binary Quantized Phase Detector
r
NRZ data is sampled at each bit cell and near the
transitions of each bit cell
The sign of the transition sample is compared with the
preceeding and following bit cell sample to deduce the
phase error
A T B
D Q
D Q
D Q
D Q
A
T
B
Data
Clock
A
T
B
Output
0
0
0
tristate
0
0
1
vco fast
0
1
0
?
0
1
1
vco slow
1
0
0
vco slow
1
0
1
?
1
1
0
vco fast
1
1
1
tristate
[Ale75][WHY91][LaW91][ReG73]
31
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D Q
simplified schematic symbol:
clock
Decision Circuit
Quantizes amplitude at precise sample instant
Typically uses positive feedback to resolve small input
signals
A master/slave D-flip-flop carefully optimized for input
sensitivity and clock phase margin is a common choice
Latches data on the rising edge of clock signal
32
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Example Bipolar Decision Circuit
data in
clock in
Vbias
data out
-5V
master latch
slave latch
gnd
many clever optimizations are possible
[OhT83][Con84][Lai90][Run91][Hau91][Run91]
33
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Loop Filters
UP
DOWN
V
OUT
UP
DOWN
V
OUT
0
0
tristate
0
1
ramp DOWN
1
0
ramp UP
1
1
tristate
[Den88] [Dev91]
[LaW91] [WuW92]
should have provision for holding value constant (tri-
stating) under long run-length conditions
may be analog (integrator) or digital (up-down
counter) - but
w
a
t
c
h
o
u
t
f
o
r
m
e
t
a
s
t
a
b
i
l
i
t
y
!
34
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Metastability
DT
DV
e
D
Q
slope = dv/dt
For uniform clock jitter, and a latch “danger zone”of ,
the metastability probability
, is
.
e
p
metastability
e
DT
-------
dt
dv
×------
35
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VB.NET PowerPoint: VB Code to Draw and Create Annotation on PPT
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Regeneration time constant t
time [ns]
0.0
0.5
-1.0
0.0
1.0
2.0
3.0
0.0
-8.0
v
diff
log
10
(v
diff
)
v
o
l
t
s
l
o
g
1
0
(
v
o
l
t
s
)
v=e
v
diff
Asmall voltage e is forced on latch, until t=0. Differential
voltage
grows as
.  For a given
and ,
the regeneration time required is
.
V
diff
e
t⁄
×
V
min
e
t
V
min
e
-------------
Ł
ł
æ
ö
×log
36
SPICE tip: current-controlled R/switch
# SPICE time variable resistor.
# the resistance between %in and %out is numerically
# equal to the current pulled out of %ic
.SUBCKT tvres %in %out %ic
h1 %inx %outx poly(2) vx vc 0 0 0 0 1
rdamp %out %outx 0.001
vx %inx %in 0
vc %ic 0 0
.ENDS
in
out
i
in
ic
R = i
in
* 1 W/A
ic
vc
vx
in
out
h1
v(h1)=i(vx)*i(vc)*1 W/A
36a
VCO alternatives
s
[Cor79, Ena87, Wal89, DeV91, Lam93, WKG94]
LC Oscillator
Multivibrator
Ring Oscillator
Speed
Technology Dependent 1-10’s of GHz, CMOS 1-2 GHz
Phase Noise
Good
Poor
Integration
Poor
(L, Varactor)
Excellent
Tunability
Narrow/Slow
Wide/Fast
Stability
Good
Poor
(needs acquisition aid)
Other
Multi-Phase
Clocks
After Todd Weigandt, B. Kim, P.Gray, “Timing Jitter Analysis for High-Frequency CMOS Ring Oscillators”, March 10, 1994
37
Multivibrator VCO
I
tune
Capacitor is alternately charged and
discharged by constant current
Tuned by varying I
tune
in current source
Diode clamps keep output voltage
constant independent of frequency
Relies on non-linear switching for
oscillation behavior, and so is limited to
moderate frequencies.
Frequency =
I
tune
4CV
be
-----------------
After Alan B. Grebene, “Analog Integrated Circuit Design”, Van Nostrand Reinhold, 1972, pp 313-315
38
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