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Example Ring Oscillator VCO
Input 1
Input 2
Output
[SyA86]
[EnA87]
[Wal89]
Input 1
Tune
Input 2
Tune
I
n
p
u
t
1
I
n
p
u
t
2
Output
Output
39
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VCO injection locking (problem)
40
t
Vtune
Vcc
Noise glitch
Noise coupling back to VCO
propagation delay
t
high VCO
nom VCO
slow VCO
delayed
glitch
most VCO’s
s
a
m
p
l
e
the tune
voltage once per cycle - down
converting the system noise.
PLL: F
osc
aV
tune
aq
error
ILO: F
osc
a V
tune
aq
error
VCO can
i
n
j
e
c
t
i
o
n
l
o
c
k
to its own
delayed signal more rapidly than
to input data!
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VCO injection locking (a solution)
41
Decompose the
loopfilter pole/zero
into two separate
tuning inputs:
awiderangeinput
with very low
bandwidth
a narrow tuning
range input with
wide BW.
this greatly reduces
effect of VCO noise
on tuning curve.
S
VCO
low gain, wide BW
high gain, low BW
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False or Harmonic Locking to Data
42
data
clock
4/3 clock
2x clock
1/2 clock
correct early
late correct
early/late indications
cancel in loop filter,
leaving an attenuated,
but possibly stable lock
signal.
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Aided Acquistion
Tricky task due to Nyquist sampling constraints caused
by stuttering data transitions
Still subject to false lock if VCO range is too wide
PD
loop filter 1
loop filter 2
FD
VCO
Input Data
43
After Behzad Razavi: “Monolithic Phase-Locked Loops, ISSCC96 Tutorial”
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Training Loops
1/256
VCO
State
Machine
PDET
FDET
SEL
charge
pump
Input
Data
Reference Clock
flock
dlock
dtrans
LOS
Clock/256
Clock
2.488GHz/256
divider
bang-bang drive
retimed data
An increasingly common technique is to provide a
reference clock to the CDR circuit. This allows the VCO
process-variationtobedynamicallytrimmedout,avoiding
false locking problems.
[WSY97]
44
Phasor Diagram
Graph of relative phase between clock and data
Each complete rotation is 1 unit interval of phase slip
Rotations/second = frequency error (in Hz)
90°
270°
180°
Plot of data transitions
versus VCO clock phase.
Data at 1/2, or VCO at 2x,
the proper frequency look
locked. This puts a limit on
VCO tolerance to prevent
false locking.
= missing transitions
= actual transitions
45
dq/dt =DF
Example Lock Detector
90°
270°
180°
D
D
Q
Q
ideal data eye
noisy data eye
clock a,b
data
Raw out-of lock
indication
[WSY97]
46
20G
10G
5G
2G
1G
500M
200M
100M
50M
20M
1988
1990
1992
1994
1996
1998
4X
10X
8X
2X
8x
S
i
B
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p
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a
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T
r
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n
d
(
0
.
0
5
-
0
.
4
f
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)
C
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(
0
.
0
5
-
0
.
4
e
f
f
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c
t
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v
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f
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)
20M
10M
5M
2M
1M
500K
200K
100K
50K
20K
S
e
r
i
a
l
L
i
n
k
S
p
e
e
d
I
n
t
e
r
n
e
t
H
o
s
t
C
o
u
n
t
Si Bipolar
CMOS
CDR
only
Year of Publication (ISSCC)
I
n
t
e
r
n
e
t
H
o
s
t
C
o
u
n
t
Communication Trends
47
?
Multiphase Receiver Block Diagram
f
T
-doubler
data amplifier
phase-
detector/
state
machine
multi-phase clock generator
(VCO + interpolator)
4:16 demultiplexer
Data input
loop
filter
LOS
16
data
clock
Reference Clock
2.5GHz/128
0
o
90
o
180
o
270
o
45
o
22
o
67
o
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
0 1 2 3
[WHK98]
48
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