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DLL vs PLL which is “best”?
DLLs do not filter input reference jitter, but do not
accumulate VCO phase errors - best for clock
synthesizers running from clean reference.
PLLs can have higher phase noise because of multiple
passesthroughthedelaygatesofVCO,howeverisable
to filter noisy input signals.
49
t
delayline
Degraded clock period
ck
ck
1 2 3 4
1
2
3
4
1
2
3
[KWG94]
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Jitter Measurements
SONET has the most complete set of jitter
measurement standards, but the techniques are
useful and relevant for datacom applications also
Jitter Tolerance
Jitter Transfer
Jitter Generation
50
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Jitter Tolerance Test Setup
sinewave
generator
retiming
circuit
bit error
rate tester
decision
circuit
xamp+
limiter
data
generator
FM
modulated
clock
laser
r
transmitter
optical
l
receiver
optical
attenuator
At each frequency, the sinewave
modulationamplitudeisincreaseduntil
the BER penalty is equal to that
caused by 1dB optical attentuation
After Trischitta and Varma: “Jitter in Digital Transmission Systems”
51
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SONET Jitter Tolerance Mask
Data Rate
f
0
[Hz]
f
1
[Hz]
f
2
[Hz]
f
3
[kHz]
f
t
[kHz]
155 Mb
10
30
300
6.5
65
622 Mb
10
30
300
25
250
2.488 Gb
10
600
6000
100
1000
10 Gb
?
?
?
400
4000
f
0
f
1
f
2
f
3
f
t
15 UI
1.5 UI
0.15 UI
acceptable
range
from SONET SPEC: TA-NWT-000253 Issue 6, Sept. 1990, fig 5-13
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Jitter Transfer Measurement
retiming
circuit
decision
circuit
data
generator
network
analyzer
clock
Signal
Generator
IN
OUT
j
Phase
detector
Phase
modulator
D.U.T.
[TrV89] [RaO91]
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Jitter Transfer Specification
n
f
c
P[dB]
slope = -20 dB/decade
acceptable
range
Data Rate
f
c
[kHz]
P[dB]
155 Mb
130
0.1
622 Mb
500
0.1
2.488 Gb
2000
0.1
This specification is
intended to control
jitter peaking in long
repeater chains
54
Jitter Generation
retiming
circuit
computer
decision
circuit
S.U.T.
spectrum
analyzer
recovered
clock
55
Jitter Generation (cont.)
)
c
l
o
c
k
a
m
p
l
i
t
u
d
e
sideband
r
e
s
u
l
t
a
n
t
DQ
1) Measure Jitter Sidebands around Clock
2) Multiply Jitter components by Filter Mask
3) RMS sum total noise voltages over band
4) Convert RMS noise voltage to RMS jitter
Jitter
pp rads
(
)
2DQ
=
2
V
sideband
V
clock
--------------------------
Ł
ł
ç
÷
æ
ö
atan
@
OC-48 (2.488 Gb/s SONET) specifies 12 kHz hipass filter,
and maximum 0.01 UI RMS integrated jitter.
56
Why bother with a BB loop?
itmaybedifficulttomaintainoptimumsamplingpoint
with traditional PD/PLL or  with filter method over
process, temperature and supply variation
Narrow pulses of linear PD’s may not work well at
extremely high bit rates
for monolithic implementation, BB PD has excellent
match between retiming latch and PD latch - allows
for operation at highest latch toggle frequency
57
DQ
DQ
DQ
DQ
A
T
B
data
clk
D Q
PD
filter
VCO
data
Simple first-order BB loop
D
Q
VCO
VCO runs at two discrete frequencies:
.
Phase error is evaluated at a discrete time interval
.  In the general case, this can be considered
approximately equal to mean transition time of the
data.
f
nom
f
bb
t
update
t
update
58
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