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Stability with run-length & latency
0
e
D
1
D
0
e
2
/x - Se
Slope(t=0) = S
For bounded convergence and stable operation, the
overshootD
1
must  be less than or equal to the
undershootD
0
.  This condition is guaranteed if
x > 2e
(e is the loop update latency normalized to t
update
)
89
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Effect of BB/charge-pump tristating
90
timestep [normalized to bit time]
-15
-10
-5
0
5
10
15
j
i
t
t
e
r
[
n
o
r
m
a
l
i
z
e
d
t
o
q
B
B
]
8880
8920
8960
9000
-4
0
4
8
12
tristating doesn’t change
vco frequency when no
transition in the data.
Untristatedloophaspeak
jitter
r
u
n
-
l
e
n
g
t
h
times
worse than tristated loop
tristated loop
non-tristated
(
simulated with
x=100,
p
transition
= 50% )
0
1000
2000
3000
4000
5000
6000
7000
8000
9000 10000
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Public Domain Tools
Linux(afreeUNIXcloneforINTELx86platforms)-Excellent
platform for creative circuit design and simulation.  See
www.cheapbytes.com for a $1.95 distribution CD.
Homepage:http://www.linux.org/
Documentation:http://sunsite.unc.edu/mdw/LDP
Scientific Apps: http://SAL.KachinaTech.COM/index.shtml
ACS Circuit simulator
EOS Electronic Object Simulator
Berkeley SPICE 3f5 (bsim3 models)
SCEPTRE
91
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Summary
A lot of complexity for a “simple” system...
It’s more of an art than a science
After understanding:
the components,
the block diagrams,
the problems and the attempted solutions,
and the unique needs for your application,
Then it’s time to have fun!
92
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7%
26%
3%
23%
3%
(disk 3%)
0.5%
numbers estimated from ~250 attendees at February 1997 ISSCC CDR tutorial
CDR Application Space
Telecom
Datacom
Copper
Radio
Fiber
IR
coax
tp
pcb
Other
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CDR Design Checklist
R
C
W
0
1
/
1
5
/
9
7
,
u
p
d
a
t
e
d
9
/
1
8
/
9
8
1) Eye Margin
how much noise can be added to the input signal while maintaining target BER?
(voltage margin)
HowfarcanclockphasealignmentbevariedwhilemaintainingtargetBER?(phase
margin)
how much does the static phase error vary versus frequency, temperature and
process variation?
Is input amplifier gain, noise and offset sufficient?
2) Jitter Characteristics
what is the jitter generation? (VCO phase noise, etc)
what is the jitter transfer function? (peaking and bandwidth)
what is the jitter tracking tolerance versus frequency?
3) Pattern Dependency
how do long runlengths affect system performance?
is bandwidth sufficient for individual isolated bit pulses?
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are there other problematic data patterns?  (resonances)
does PLL bandwidth, jitter, and stability change versus transition density?
4) Acquisition Time
what is the initial, power-on lock time?
what is the phase-lock aquisition time when input source is changed?
5) How is precision achieved?
are external capacitors, inductors  needed?
does the CDR need an external reference frequency?
are laser-trimming or highly precise IC processes required?
6) Input/output impedance
Is S11/S22 (input/output impedance) maintained across the frequency band?
are reflections large enough to lead to eye closure and pattern dependency?
is  >15 dB return loss maintained across the band?
7) Power Supply
does the CDR create power supply noise?
how sensitive is the CDR to supply noise?
Is the VCO self-modulated through its own supply noise?  (can be “deadly”)
what is the total static power dissipation?
what is the die temperature under worse case conditions?
8) False lock susceptibility
can false lock occur with particular data patterns?
are false lock conditions be detected and eliminated?
does the phase detector have VCO frequency leakage  that can cause injection
locking?
can the VCO run faster than the phase/frequency detector can operate?  (another
“killer”)
have all latchup/deadly embrace conditions been considered and eliminated?
References
[Ale75]
Alexander,J.D.H.,ClockRecoveryfromRandomBinarySignals,ElectronicsLetters11,22(30thOctober1975),541-542.{binary
quantized phase detector}.
[AFD87]
Andrews, G. E., D. C. Farley, S. H. Dravitz, A. W. Schelling, P. C. Davis and L. G. McAfee, A 300Mb/s Clock Recovery and Data
RetimingSystem,ISSCCDigestofTechnicalPapers,1987,188-189.{SAWFilterClockRecoverywithemphasisonphasealignment
problem}.
[Arm83]
Armitage, C. B., SAW Filter Retiming in the AT&T 432 Mb/s Lightwave Regenerator,Conference Proceedings:AT&T Bell Labs.,
Holmdel, NJ, USA, September 3-6, 1984, 102-103. {matches tempco of SAW to tempco of electronics.}.
[Baa86]
Baack, C., Optical Wide Band Transmission Systems,CRC Press Inc., 1986. {example of PLL for clock recovery}.
[Buc92]
Buchwald et al., A., A 6GHz Integrated Phase-Locked Loop using AlGaAs/GaAs Heterojunction Bipolar Transistors,ISSCC Digest
of Technical Papers, 1992, 98,99,253. {Frequency multiplying ring oscillator}.
[Byr63]
Byrne et al., C. J., Systematic Jitter in Chain of Digital Regenerators,The Bell System Technical Journal, November 1963, 2679.
{clock extraction by filtering}.
[CCI90]
CCITT, Digital Line systems based on the synchronous digital hierarchy for use on optical fiber cables, CCITT G.958, 1990.
{SONET Payload test patterns regenerator scrambling}.
[Car56]
Carter, R. O., Low-Disparity Binary Coding System,Electronics Letters 1, 3 (May, 1956), 67-68. {conditional inversion data encod-
ing disparity}.
[Cho92]
Chona,F.M.R.,DraftStandard,SONETinter-officeandintra-officelinejitterre., T1X1.3,May11,1992.{StandardsSONETjitter}.
[Con84]
Connor et al., P. O., A Monolithic Multigigabit/Second DCFL GaAs Decision Circuit,IEEE Electron Device Letters EDL-5, 7 (July
1984), 226-227. {GaAs Fet decision circuit example}.
[Cor79]
Cordell et al., R. R., A 50MHz Phase and Frequency Locked Loop,IEEE Journal of Solid State Circuits SC-14, 6 (December 1979),
1003-1009. {quadricorrellator phase detector, Tunable LC Oscillator}.
[DR78]
D’Andrea, N. A. and F. Russo, A Binary Quantized Digital Phase Locked Loop: A Graphical Analysis, IEEE Transactions on Com-
munications COM-26, 9 (September 1978), 1355-1364. {Analysis of BB loop}.
[DeV91]
DeVitoetal.,L.,A52MHzand155MHzClock-RecoveryPLL,ISSCCDigestofTechnicalPapers,February13-15,1991,142,143,
306. {multivibrator example, Negative resistor chargepump, rotational freq.det.}.
[Den88]
DenDulk,R.C.,DigitalFastAcquisitionMethodforPhase-LockLoops,ElectronicsLetters24,17(18thAugust1988),1079-1080.
{2 order of magnitude locking speed-up with fancy slip detector & charge pump}.
[EnA87]
Enam,S.K.andA.A.Abidi,DecisionandclockRecoveryCircuitsforGigahertzOpticalFiberReceiversinSiliconNMOS,Journal
of Lightwave Technology LT-5, 3 (March 1987), 367-372. {MOS tunable monolithic ring oscillator example - Some clever circuit
ideas for gigabit rates}.
[EnA92]
Enam,S.K.andA.A.Abidi,MOSDecisionandClockRecoveryCircuitsforGb/sOptical-FiberReceivers,ISSCCDigestofTechni-
cal Papers, 1992, 96,97,253. {quadratic phase detector} {MOS decision circuit example}.
[FHH84]
Faulkner, D. W., I. Hawker, R. J. Hawkins and A. Stevenson, An Integrated Regenerator for High Speed Optical Fiber Transmission
Systems,IEE Conference Proceedings (November 30 - December 1, 1983) 8-13. {uses rectifier/SAW combo}.
[FLS63]
Feynman, R., R. B. Leighton and M. Sands,The Feynman Lectures on Physics, Addison-Wesley Publishing Company, 1963. {Short,
simple presentation of timestep analysis for planetary motion}.
[FMW97] Fiedler, A., R. Mactaggart, J. Welch and S. Krishnan, A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-
Emphasis,ISSCC Digest of Technical Papers 40(February 6-8 1997), 238,239,464. {transmit pre-emphasis, skin loss equalizer}.
[Gal94]
Galton, I., Higher-order Delta-Sigma Frequency-to-Digital Conversion,Proceedings of IEEE International Symposium on Circuits
and Systems (May 30 - June 2, 1994) 441-444 {Delta-Sigma BB loops phase tracking frequency digitalization PLL}.
[Gal95]
Galton, I., Analog-Input Digital Phase-Locked Loops for Precise Frequency and Phase Demodulation,Transactions on Circuits and
Systems-II: Analog and Digital Signal Processing42, 10 (October 1995), 621-630. {good discussion of delta-sigma analysis of BB
PLL’s}.
[Gar79]
Gardner, F. M.,Phaselock Techniques, Second Edition, John Wiley and Sons, Inc., 1979. {example of using exor-gate to generate
clock component from NRZ data}.
[Gla85]
Glance, B. S., New Phase-Lock Loop Circuit Providing Very Fast Acquistion Time,IEEE Transactions on Microwave Theory and
Techniques MTT-33, 9 (September 1985), 747-754. {adds non-linear time constant to speed PLL acquisition by 2 orders of mag.}.
[Gri69]
Griffiths, J. M., Binary Code Suitable for Line Transmission, Electronics Letters 5, 4 (February 20, 1969), 79-81. {5b/6b encoding
example}.
[GMP78] Gruber, J., P. Marten, R. Petschacher and P. Russer, Electronic Circuits for High Bit Rate Digital Fiber Optic Communication Sys-
tems,IEEE Transactions on Communications COM-26, 7 (July 1978), 1088-1098.
[Gup75]
Gupta, S. C., Phase-Locked Loops, Proceedings of the IEEE 63, 2 (February 1975), 291-306. {Good systematic outline survey of
communication-type PLL’s}.
[Hau91a]
Hauenschild et al., J., A Silicon Bipolar Decision Circuit Operating up to 15Gb/s,IEEE Journal of Solid State Circuits 26, No.11
(November 1991), 1734-1736. {Si bipolar decision circuit example}.
[Hau91b] Hauser,M.W.,PrinciplesofOversamplingA/DConversion,J.AudioEng.So.Vol39,1/2(Jan/February1991),3-26.{excellenttuto-
rial on Delta Sigma AD, Oversampling, noiseshaping}.
[HeS88]
Hein,J.P.andJ.W.Scott,z-DomainModelforDiscrete-TimePLL’s, IEEETransactionsonCircuitsandSystems35,11(November
1988), 1393-1400. {good discussion of using z-transforms in PLL analysis}.
[Hog85]
Hogge, Jr., C. R., A Self Correcting Clock Recovery Circuit,IEEE Transactions on Electron Devices ED-32, 12 (December 1985),
2704-2706. {Original Hogge detector, interesting phase detector idea...}.
[Hor92]
Hornak, T., Interface Electronics for Fiber Optic Computer Links,Intensive Course on Practical Aspects in Analog IC Design, Lau-
sanne, Switzerland, June 29-July 10, 1992. {Excellent overview of components for serial optical data transmission}.
[Hu93]
Hu, T. and P. Gray, A Monolithic 480 Mb/s AGC/Decision/Clock Recovery Circuit in 1.2 um CMOS,IEEE Journal of Solid State
Circuits 28, 12 (Dec. 1993) 1314-20 {CMOS parallel signal paths multiphase sampling CDR mux}.
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