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High Speed Analog Design and Application Seminar
3-11
Texas Instruments
Analog Input Sample & Hold Amplifier Circuit
The sample and hold amplifier is implemented using switched cap techniques. A
simplified functional block diagram is shown here. The SHA is in sample mode
when the clock is high and in hold mode when it is low. In sample mode the F1
switches are closed and the differential input signal is sampled onto the
capacitors Cs. As the CLK falling edge occurs, the F1 switches are opened and
the SHA is now placed into hold mode. The F2 switches are subsequently closed,
and the voltage across the sampling capacitors is then transferred to the output of
the S/H amplifier.
ADC Simplified Input Circuit
ø1
ø1
ø2
Input Clock
Internal  Clock, 
non-overlapping
t
CONV
ø1
ø2
ø1
ø1
ø1
Out
Out
IN
IN
C
S
V
CMi
C
S
V
CMi
ø2
V
CMi
= internal common-mode voltage
Differential Sample & Hold (Flip-around)
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High Speed Analog Design and Application Seminar
3-12
Texas Instruments
Because the input to the sample and hold amplifier is a switched capacitor circuit, the input
impedance is dynamic and dependent upon the sampling rate of the converter. The effective
resistance of the dynamic load for each input is defined by the following equation.
Input Impedance: Z
in
= 1 / (F
s
* C
s
)
Where C
s
= Sampling Capacitor; F
s
= Sampling clock frequency in Hz; Ron = ON resistance of
MOS switch
Z
in
: - High Static
(no clock) Input Impedance, >1Mohm
- Dynamic
Input Impedance Proportional to Sampling Clock
Small sampling capacitor values allow for very fast charging times, which corresponds to fast
acquisition times. However, the trade-off here is the noise. The generated switching induced
noise is equivalent to en= √kT/C
s
. It can easily be seen that reducing the sampling capacitor
value is reciprocally affecting the noise.
The components R
on
and C
s
also determine the ADCs ‘Analog Input Bandwidth’, a topic that will
be discussed later in this seminar.
The time averaged charging of the sampling capacitor will cause a net dc current to flow into the
ADC’s input. The magnitude of this current changes depending on the clock frequency. Current
(I
in
) inrush to charge C
s
to V
in
. Q = C
s
* (V
in
– V
cm
)
The implementation of this transmission gate type switch typically includes the use of
‘bootstrapping’. The purpose is to maintain a constant VGS on the transistors and linearize the
voltage dependency of the on resistance. This will help minimizing the distortion generated. This
is particularly critical for IF sampling applications. Another advantage is that the ADC’s
performance becomes less sensitive to the external common-mode voltage.
ADC Input  -  Switched Capacitor
ø1
CLK
H
ø2
CLK
L
VIN
C
S
V
CM
(Parasitic
Capacitance)
C
P
Z
IN
I
IN
R
ON
1
fcC
R
Z
s
ON
IN
+
=
ADC
1
fcC
R
s
ON
<<
Typically:
Example: C
s
= 5pF
Z
in
~ 2000Ω @ 100Msps
Z
in
~ 20kΩ @10Msps
Load to the driving Source !
Equivalent Input Impedance:
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High Speed Analog Design and Application Seminar
3-13
Texas Instruments
During the sampling phase (typically half the clock period) the driving source must
charge or discharge the sampling capacitors to the new value. The condition
encountered by the driver is a rapid change of its load and it must recover from this
transient and settle to the new value. The worst case would be a full-scale excursion,
but in most cases the input slew rate is significantly less. But even in this case the
instantaneous demand of charging current could be challenging for a driver, e.g. an
op amp, especially since the signal should be settled to within ½ LSB.
Unsymmetrical or incomplete settling will result in an increase in distortion and
reduction in the achievable SFDR performance. Ideally, the source impedance seen
by the inputs of the high-speed ADC should be low and constant over a wide
bandwidth.
Most ADC input driver configurations benefit from adding low value series resistors
at the inputs of the ADC as well as shunt capacitors. Those simple components can
be instrumental in achieving the listed requirements.
Driving the ADC Input
ɿ
Driver must charge or discharge ADC sampling cap to
the new input voltage
ɿ
Settle to ½LSB in the sample period of f
s
/2
ɿ
Differential Inputs require Symmetrical Settling
ɿ
Incomplete Settling  may degrade SFDR performance
ɿ
Source Impedance looking back from the ADC should
be low up to high frequencies
Input Driver Requirements
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High Speed Analog Design and Application Seminar
3-14
Texas Instruments
This slide describes the use and functions of the series resistors, R, and the shunt
capacitors ,C. References to the resistors and capacitors as shown here can be
found in most product datasheets as a means to optimize the performance of input
driver configuration for pipeline ADC. While the values may be different their use is
typically recommended for transformer based as well as amplifier based circuits.
Driving the ADC Input – R & C
Insert Series Resistor, R
ɿ
Reduces peak transient current
ɿ
Decouples driver from capacitive ADC input
(improves settling time due to reduced ringing)
Add Shunt Capacitor, C
ɿ
Supplies/absorbs charge from internal Cs during
sampling phase
ɿ
Shunts switching related current transients to ground
Cs
S/H
R
R
C
C
IN
IN
Optimizing Driver Performance
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High Speed Analog Design and Application Seminar
3-15
Texas Instruments
Driving the ADC Input – R & C
ɿ
Results in 1
st
order RC low-pass Filter
ɷ
Limits Wideband Noise to the ADC
ɷ
Noise Bandwidth, NBW = π/2 x 1/(2 πRC)
ɷ
Higher Order LP/BP-Filter possible
ɿ
Typical Values
ɷ
R: 10 to 100ohm typ.
ɷ
C: 1 to 100pF typ
ɿ
Values should be optimized based on
ɷ
Input Frequency and Sampling Rate (ADC model)
ɷ
Application; Time-Domain, Frequency-Domain
ɷ
ADC and OPA Datasheet Recommendations
The R and C together form a simple real-pole low-pass filter. Placing this pole at
about 10 times the highest frequency of interest ensures that it has no adverse
affect on the signal and driving source. For example, at the pole frequency the
amplifier sees a load equal to v2 R. With the resistor value being as low as
10ohm, the amplifier output would be heavily loaded resulting in a significant
increase in distortion.
Noise Bandwidth refers to a brick-wall filter frequency response. To account for
the difference in the -3dB bandwidth of this first-order RC filter (BW=1/(2πRC))
and the Noise Bandwidth a factor of π/2 is used.
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High Speed Analog Design and Application Seminar
3-16
Texas Instruments
Optimizing the ADC Interface
Observations:
ɿ
Increasing R and/or C
ɷ improves SNR, due to lower f 
–3dB
point of RC-LP
ɷ reduces SFDR, due to longer settling time
¾Note:
ɷ R’s have 1% tolerance typ.
ɷ C’s have 10% tolerance typ.
SNR
SFDR
Trying to optimize the interface circuit including the adjustments of the R and C
values the designer should be aware of their effects and the resulting constraints.
Generally, the values can only be changed within a certain range before the
ADC’s performance is negatively impacted. Also, choosing component values
that seem to improve the SNR may carry a penalty on the distortion and SFDR
performance, and visa versa. In the context of differential signaling attention
should be paid to the component tolerances as it may lead to unsymmetrical
settling times.
High Speed Analog Design and Application Seminar
3-17
Texas Instruments
In addition to selecting the right values of R
s
and C
s
for the chosen ADC model and
application, their configuration might be of importance as well. Shown here are the
two common configurations one can also find in the product datasheets. While the
circuit on the right uses two shunt capacitor in a single-ended configuration the left-
hand circuit example employs only one capacitor placed across the inputs of the
ADC. At the same time its value is reduced by half to maintain the same time
constant.
Designers considering to use the left-hand implementation should pay close
attention to the ground connection of the two shunt capacitors. If their ground is
noisy or carries other interferences such signals can be directly coupled into the
signal path resulting in reduced performance (e.g. higher noise). Both capacitors
should be grounded to the same low-noise ground point such that any frequency
coupled in occurs as a common-mode signal and can be suppressed by the ADCs
common-mode rejection.
Driving the ADC Input
R
1
R
2
C
1
C
2
IN
IN
Critical ground node – view as ‘signal input’ during pcb layout
C/2
IN
IN
ADC
ADC
Important Considerations:
ɷ Match RC time constants (R
1
C
1
=R
2
C
2
) for optimal differential signaling
ɷ Match pc-board trace length
R
1
R
2
RC Input Filter
High Speed Analog Design and Application Seminar
3-18
Texas Instruments
Working with the ADC Input
High Speed Analog Design and Application Seminar
3-19
Texas Instruments
ADC – Analog Input Bandwidth
Common Definition:
ɿ
The analog input frequency at which the spectral
power of the fundamental frequency (as determined
by the FFT analysis) is reduced by 3 dB.
Alternative Definition:
ɿ
“Effective Resolution Bandwidth”, (ERB)
ɿ
The analog input frequency at which the ENOB
(SINAD) is reduced by 0.5Bit (3dB), based on an
FFT.
Analog Input Bandwidth definition as it is used on high-speed ADCs:
The analog input frequency at which the spectral power of the fundamental
frequency (as determined by the FFT analysis) is reduced by 3 dB. Depending on
the manufacturer the Analog Input Bandwidth may be based on a small-signal or
full-scale input amplitude. Consequently, the specified numbers can vary widely.
In this context the Analog Input Bandwidth of the ADC is mainly determined by
the Ron-resistance of the input switch and the size of the sampling capacitor.
It should be noted that the Analog Input Bandwidth is a rather theoretical number
because it does not describe how well the ADC maintains its ac-performance.
SFDR, SNR, THD and ENOB performance curves should be analyzed to
determine the ac performance.
An alternative definition of the Analog Input Bandwidth that is based on the ADCs
decline in performance is the ‘Effective Resolution Bandwidth’.
High Speed Analog Design and Application Seminar
3-20
Texas Instruments
ADC – Analog Input Bandwidth
ɿ
Large Signal vs Small Signal
ɿ
Input S&H of ADC determines the input
bandwidth
ɿ
Full-Power Bandwidth is directly related to
the Full-Scale Input Range of the ADC
ɿ
FPBW is a ‘theoretical’ number
Analog Input Bandwidth
The S&H performance of an ADC is the most significant function that
determines the input bandwidth:
The slew-rate capability of the S&H determines the ‘Full-power
Bandwidth’ (FPBW) for large signals, typically with the input
amplitude set near full-scale (-1dBFS).
The frequency response of the S&H determines the small signal
bandwidth for small signals. The input signal amplitude is
significantly below FS, for example at -20dBFS.
Typically, when specifying the ‘Analog Input Bandwidth’ of an ADC, it is
based on the Full-Power Bandwidth. It is directly related to the full-scale
input range of the ADC and therefore can be used as an initial selection
criteria
when comparing converter for their undersampling capabilities.
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