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High Speed Analog Design and Application Seminar
3-21
Texas Instruments
ADC – Analog Input Bandwidth
G - Gain - dBFS
0
-2
-4
-6
-8
-10
1
10
100
1000
f - Input Frequency - MHz
ADS5421
FPBW approx. 550MHz
ADS5421
14-bit , 40MSPS  Pipeline ADC
fs
fs/2
Shown here is the frequency response of the ADS5421, a 14-Bit, 40Msps
pipeline A/D converter as an example of its ‘Analog Input Bandwidth’. This
CMOS converter uses a differential sample-and-hold circuit. The switched
capacitor architecture allows for a very wide analog input bandwidth.
Also indicated by the red line markers are the Nyquist frequency at 20MHz,
and the sampling frequency at 40MHz.
The information obtained out of such a bandwidth is that one can estimate
the attenuation to the input signal based on the ADCs frequency response.
For example, inputting a 200MHz signal into the ADS5421 would cause an
attenuation of about 0.5dB.
Again, there is no indication on what the dynamic performance will be at
this high input frequency. Specifying an ‘Effective Resolution Bandwidth’
would make this connection.
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High Speed Analog Design and Application Seminar
3-22
Texas Instruments
4V
Over-range condition
Sample taken
2.5V
6 Clock cycle
latency
n
n+1
n+2
n
n+1
n+2
Sample is
over-range,
invalid data
Valid data
Valid data
output
data
clock
Input
1V
ADC – Input Overload Recovery
OVERVOLTAGE RECOVERY TIME
There is no one condition, except that the signal amplitude must stay below the
supply voltage. If the ADC has internal ESD diodes on its inputs they may start to
conduct. For most CMOS based design this is usually 0.3V above and below the
supply rails. If the input voltage exceeds the full-scale range of the ADC the input
capacitors of the input S&H are still being charged to reflect that value. Assuming
now, the overload condition instantly disappears, within one clock cycle the
charge on the input caps will be removed and biased back to a normal value. It
will take as many pipeline delays as the converter has until valid data is available
on the data outputs. In this example it will take 6 clock cycles.
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High Speed Analog Design and Application Seminar
3-23
Texas Instruments
ADC – Input Overload Recovery
ɿ
Vinput < Vsupply
Peak input voltage exceeds specified full-scale ADC input range,
but remains within the supply rails:
ɷ
ADC output at all ‘1’ or ‘0’ during overload
ɷ
Once overload condition removed, ADC acquires new valid
sample with the next clock cycle
ɿ
Vinput > Vsupply
Peak input voltage exceeds the supply rail(s):
ɷ
ADC output at all ‘1’ or ‘0’ during overload
ɷ
Internal ESD diodes may conduct and short circuit signal
DC-coupled input configuration:
ɷ
Possible excessive current flow
ɷ
Possibility of damage – need to add external protection, e.g. R’s
and diodes, or Voltage Limiting Amplifier (e.g.OPA698)
Two cases:
When the input voltage at any pin exceeds the power supplies (that is,
V
IN
< AGND or V
IN
> VA or VD), the current at that pin should be limited to less
than 10mA.
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High Speed Analog Design and Application Seminar
3-24
Texas Instruments
ADC References
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High Speed Analog Design and Application Seminar
3-25
Texas Instruments
High-Speed ADC References
ɿ
Internal References
ɷ Typically designed to meet ac specs
ɷ Not a ‘precision’, low-drift Reference
ɷ Limited drive capability
ɷ Inherently good matching for multi-channel ADCs, e.g. octal
ADS5121
ɿ
External References
ɷ May be used to improve gain matching between devices
ɷ Typically complex circuit
• Needs high-speed properties
• Drive capability and Cload stability
• May not be tracking; Range, drifts
Often the specification around the internal references are scarce. In some cases
the reference performance is included in the overall ADC specifications such as
gain error, or gain error drift.
In other instances errors caused by the references are separated from the rest of
the converter. For example, the ADC may have a gain error spec which is based
on operating it in the external reference mode. In order to understand the total
gain error one would have to combine the ADC error and the reference error.
In most cases the ADC and its reference form an entity designed primarily to
achieve the ac-performance goals. DC precision is usually compromised. This
might be a limitation especially for dc coupled time domain applications. The drift
performance of the internal reference is typically moderate with around 20ppm/°C.
Also, the internal references are designed to accommodate the demands of the
ADC core. There is usually very little drive capability left to supply any external
circuitry. In most cases external buffer are required.
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High Speed Analog Design and Application Seminar
3-26
Texas Instruments
ADC - Reference Bypassing
Very Important !
ɷ Switching Noise on
Reference lines
ɷ Need to be
bypassed to
maintain stable
Reference Voltages
ɷ Bypass close to the
pins
ɷ Use very low
inductance caps
REFT
CM
REFB
Bandgap Reference
And Buffer
RL
Bypass Capacitors: 0.1uF each
RL
RL
RL
ADC Core
(n Pipeline Stages)
Once sampled the input signal is compared to the reference voltage all throughout the
pipeline stages. The digital result of this comparison is based on the momentary ratio of
the signal to the reference.
Typically, internal to the ADC a top (REFT) and a bottom (REFB) reference voltage is
generated. Connected to those reference points are the many sample&hold stages of the
pipeline ADC core with their many switches. As these switches open and close at the rate
of the clock they generate charge injection and ultimately add to the converter’s noise. In
order to minimize the noise contribution of this clock feedthrough the reference pins
require solid high-frequency bypassing. This is usually accomplished by placing ceramic
capacitors as close to the pins as possible. The lead inductance of those capacitors
should be minimized. Choosing surface mount components in a small size (i.e. 0603,
0402 size) yield typically the best results. Depending on the converter model the addition
of low ESR tantalum capacitors may be recommended.
In addition to the bypass caps going to ground, a cap between the REFT and REFB pins
may further improve the performance.
The reference ladder typically have an impedance ranging from several kohms down to
100ohm. This should be considered when opting for external reference operation. While
the REFT and REFB nodes are in most cases buffered, the mid-point of the ladder, the
Common-mode point (CM) is usually not. Using this CM pin for biasing any input driver
circuits may be limited.
High Speed Analog Design and Application Seminar
3-27
Texas Instruments
Clock Considerations
High Speed Analog Design and Application Seminar
3-28
Texas Instruments
ADC Clock Considerations
Clock Quality a Major Factor for achieving high Dynamic
Performance!
Very low Jitter required to maintain good SNR
• Especially at high Input Frequencies (IF)
SNR
j
= 20log
2π x f
IN
x t
aj
t
aj
= rms aperture jitter
f
IN
= Input Frequency
1
• Independent Jitter Sources sum by Root-Sum square
t
ajtot
(t
ajADC
+ t
ajExt
[psrms]
The degradation in SNR is dependent on the input frequency and the total
aperture jitter.
Since jitter is a random occurrence and sources are typically not correlated
they add by calculating the square-root of the sum of the squares.
The slew-rate (dv/dt) of undersampled IF input signals is very high.
Consequently, the effect of clock jitter is pronounced and therefore
requires special consideration.
High Speed Analog Design and Application Seminar
3-29
Texas Instruments
ADC Clock Considerations
Clock ‘Quality’
ɿ
Use Differential Clock Signal
ɿ
Observe symmetry of Clock line and Impedances
ɿ
Fast rise/fall times
ɿ
Use 50% Duty Cycle at max. Sampling Rate
•  less important, if A/D operated below max. sampling rate
ɿ
Maintain Clock within the recommended range
• Amplitude (Vp-p), and Common-Mode Level (V
CM
)
• Use proper Termination Techniques to avoid Reflections
• Avoid any Over- or Undershoot
ɿ
Use higher turns ratio for Transformer coupled Circuit to increase
amplitude
Consider using logic circuits that have sufficiently fast rise and fall times
(1ns) to minimize their contribution to the total jitter error.
If this option is available, the ADC’s clock input should be driven
differentially. Applying a single-ended clock to differential clock inputs may
not yield the optimum performance due to asymmetric rsie and fall times
that will also affect the duty cycle.
If the A/D converter is operated below its maximum sampling rate the duty
cycle requirement for the converter clock may be relaxed, meaning it can
vary from the ideal 50% point.
High Speed Analog Design and Application Seminar
3-30
Texas Instruments
The Aperture Error is
less than 1 LSB, if:
Δt
A
<
1
2n × π × f
IN
t
A
V
V
P
-V
P
T
A
Δt
A
Δv
V+ Δv
Error due to Aperture-Jitter is directly proportional to dv/dt of
input signal (fin)
Aperture/Clock - Jitter
Δv  = dv/dt x Δt
A
Clock
Hold
Δta 
rms
= Aperture Jitter
Jitter is the time domain representation of clock noise.
Aperture Jitter = The rms variation in the aperture delay due to random
noise effects.
Aperture Delay = The time delay between the external sample command
(typically the 50% point of the rising clock edge) and the time at which the
signal is actually captured. Clock path propagation delays contribute
(inside the IC) to aperture delay.  Is usually considered a constant.
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