84
MEASURING AND COMPUTING DIGITAL-TO-SYNCHRO
OR DIGITAL-TO-RESOLVER CONVERTER PARAMETERS
on pages 85 and 86, the power amplifiers and output
transformer are critical elements in the overall accu-
racy-determining chain. This is particularly true if the
synchro or resolver specification allows significant
unbalance in its loading on the converter.
(Unbalance can be simulated statically by paralleling
one or more windings of symmetrical synchro or
resolver with additional resistive or reactive loads.)
The principal effects of loading on the performance
of a D/S or D/R converter are:
•
Increased nonlinearity in certain regions
•
Degradation of slew rate and data throughput rate
•
Increased drift, due to self-heating
•
Decreased absolute accuracy, due to gain loss
Figure 8.4 shows a static test setup that employs
manually switched data inputs, and a precise read-
out of shaft angle, using another synchro or resolver
transducer and a synchro or resolver angle readout
as the result-reporting instrumentation. (Clearly, the
accuracy of the instrumentation should be an order
of magnitude better than the accuracy of the con-
verter under test.)
Amplifier Mismatch Errors
Some D/S or D/R converters do not provide the
exact voltage, power, or impedance ranges
required by the synchro or resolver to be used. At
first glance, it would seem that this kind of mis-
match is unimportant, provided that the load falls
within the limits implicit in the ratings of the D/S
or D/R converter, but that is not always the case.
For example, a D/S or D/R converter rated to
deliver 90 Volts into 5,000 Ohms or more can be
used to drive a 26 Volt, 12,000 Ohm synchro or
resolver control transformer, but the slew rate,
accuracy, linearity, and possibly the data through-
put rates of the converter will be altered consid-
erably by the restricted range of operation and
the lightly loaded condition of the output amplifi-
er. These mismatch effects can usually be avoid-
ed or compensated for, by either internal or exter-
nal design modifications.
Static Errors and Instabilities
Refer to pages 79 and 80, on which this subject
has been discussed in detail for S/D or R/D con-
verters, and follow the same general procedures
for testing, substituting the test circuits given in
this section. Note that reference, power-supply,
and temperature changes have far less effect on
D/S or D/R converters than they do on S/D or R/D
converters, because almost every critical para-
meter is derived as a ratio. Even the basic refer-
ence-carrier signal cannot have a first-order
effect on accuracy, because the analog data out-
put (the angle θ) is synthesized as the ratio of two
carrier-frequency amplitudes, both derived from
the same reference input.
88
Figure 8.4.Testing D/S (or D/R) Converters Under Load.
STABLE
OSCILLATOR
Vref
INPUT
CT
PAV
DIAL
INDICATOR
(GONIOMETER)
D/S OR D/R
CONVERTER
UNDER
TEST
(INCLUDING
ANY REQ'D
AMPLIFIERS)
LOGIC
ONE
LEVEL
+
74
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
Parameter Tradeoffs vs.Price
In general (but with many exceptions and even a few
inconsistencies, notable from manufacturer to manu-
facturer), the following approximate relationships
hold true for synchro/resolver-to-digital converters:
• Price increases with accuracy, when in the range
of ±0.5 to ±1 minute.
• Price increases with operating temperature range,
for a given electrical performance. The most com-
mon ranges are 0° to +70°C, -40° to +85°C and
-55°C to +125°C. The prices for the wider ranges
are higher.
Typical Interface Circuits (Input and Output)
The following selected discussions are representa-
tive of the design considerations encountered by the
system planner in the field, but this information can-
not do more than suggest the broad range of tech-
niques possible for system optimization.
One large group of interface problems concerns syn-
chronizing the converter (S/D or D/S) with the other
elements in the system. Older S/D converters pro-
vided either a "Converter Busy" signal (CB), or a
"Data Ready" pulse (DR). This allowed the designer
to prevent data transfer or use while a conversion
was in process, thereby avoiding incorrect readings
(or invalid data). System compatibility was also
enhanced, in these S/D converters, by a Conversion
Inhibit terminal INH
, which permitted holding output
data stable during transfer. Figures 9.1a through
9.1d show various ways of using these CB, DR,
and/or INH
signals in older converters. The newer
generation of S/Ds or R/Ds have internal latches and
tri-state output buffers and are much easier to inter-
face. We will discuss these S/Ds and R/Ds later.
• The simplest method of forcing synchronization
between an older S/D converter and system timing
is to use the inhibit (INH
) line. Figure 9.1a illus-
trates this technique. In most converters with an
INH
line and Converter Busy (CB) pulse, the CB
89
SECTION IX
Z
Z
Z
3 µs
5 µs
5 µs
60* µs MIN.
DEPENDING
ON dθ/dt
"1"
"0"
"1"
"0"
CONVERTER
BUSY (CB)
INHIBIT
APPLIED (INH)
DATA TRANSFER
Figure 9.1a.Forced synchronization between
S/D and system.
Figure 9.1b.S/D Converter Timing.
S/D
INH
CB
REG.
STROBE
CPU
* 15 µs for Fast Tracking 4 rps units (14-bit resolution)
86
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
pulse will complete its cycle once it starts. The
INH
will prevent it from starting, but if CB has start-
ed before an INH
is applied, the CB will continue
to completion (generally 2-4 µs) and then strobe
the data into a register or computer for use in the
system. Figure 9.1b shows typical timing wave-
forms for such S/D converters.
• Figure 9.1c illustrates older S/D converter asyn-
chronous data transfer - i.e., data transferred to its
destination whenever the S/D converter has it
available (regardless of system timing). A flip-flop
buffer register is enabled to receive the output of
the converter (by jam transfer) when CB changes
to CB
...from logic ONE to logic ZERO. The con-
verter is then free to perform its next conversion,
leaving the previous datum in the register.
• The response of most D/S converters is extreme-
ly fast, and digital data may generally be fed into
the converter, without regard to the converter's
response time. In some cases, however, such as
in multiplexed systems, or where the D/S convert-
er is on a data bus, the data is only valid for a short
period of time. For these cases an input buffer
register must be provided, as shown in figure 9.1d.
This allows strobing the data into the converter at
the appropriate time and holding it until the next
update. Most digital data sources provide a strobe
line for entering the data into a register.
Newer D/S or D/R converters have double-buffered
input latches making the use of external registers
superfluous.
Transferring data from the newer S/Ds or R/Ds with
internal latches and tri-state buffers to 8- and 16-bit
buses is shown in Figures 9.1e through 9.1h. In
these converters the INHIBIT command will lock the
data in the output transparent latch without interfer-
ing with the continuous tracking of the converter's
feedback loop. Therefore, the counter is still allowed
to update and the inhibit can be applied for an arbi-
trary amount of time without having to worry about
reacquisition time.
90
CB
S/D
CONVERTER
MSB
MSB
LSB
LSB
BUFFER
REGISTER
TO COMPUTER,
PRINTER, ETC.
STROBE
Figure 9.1c.Asynchronous Data Transfer.
ONE-SHOT
DELAY
OR
MSB
D/S
CONVERTER
LSB
STROBE
USE
DELAYED
GATE OUTPUT
or
DELAYED
STROBE SIGNAL
FROM SOURCE
FROM DATA
SOURCE
R
E
G
I
S
T
E
R
Figure 9.1d.Eliminating the Effects of Random
Propagation Delays.
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48
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
91
RDC-19220
8-BIT BUS
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
(LSB) BIT 16
D7
D6
D5
D4
D3
D2
D1
D0
EM
EL
INH
SERIES
(MSB)
(LSB)
Figure 9.1e.Data Transfer to 8-bit Bus.
INH
DATA 1-8
VALID
DATA 9-16
VALID
300 ns MAX
150 ns MIN
100 ns MAX
150 ns MAX
100 ns MAX
EL
EM
Figure 9.1f.Data Transfer to 8-bit Bus Timing.
49
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
92
RDC-19220
16-BIT BUS
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
(LSB) BIT 16
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
EM
EL
INH
SERIES
Figure 9.1g.Data Transfer to 16-bit Bus.
INH
DATA 1-16
VALID
300 ns MAX
150 ns MAX
100 ns MAX
EM, EL
Figure 9.1h.Data Transfer to 16-bit Bus Timing.
99
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
93
Another large group of interface problems concerns
preserving the integrity of the input signals. Figures
9.2a - 9.2b illustrate several important techniques
commonly used to avoid error-inducing conditions at
the data and reference inputs of an S/D converter.
Figure 9.2a shows recommended safeguards against
the error sources that may be introduced by long-line
cabling between remote transducers and the convert-
er inputs. These error sources have all been dis-
cussed earlier (see page 69) and need only to be list-
ed here: common-mode voltages: ground-loop sig-
nals;electromagnetic pickup;and electrostatic pickup.
The remedies suggested by Figure 9.2a are as fol-
lows:
• For common-mode voltage (CMV), use of a care-
fully balanced isolation circuit, providing high
CMRR (common-mode rejection ratio). This
CMRR also attenuates ground-loop signals that
may be included in the signal path.
• For electromagnetic pickup, triple-twist shielding
of the cables and the input transformer ...and pos-
sibly of the entire converter, if the disturbing field is
very strong.
• For electrostatic pickup, shielding of the cables and
(probably) an electrostatic shield on the transformer.
• For noise, broadly tuned bandpass filtering, with
negligible phase shift in the pass band, which is
centered on the carrier frequency.
Note that Figure 9.2a implies coupling paths that are
not normally considered in high level DC input cir-
cuits, but that may become more important at 400 Hz
(and its harmonics) in high-precision devices. Note
also that the best of modern S/D or R/D converter
designs provide very well isolated, guarded and bal-
anced high-impedance input circuits. Note also that
cable impedance may be a problem, if the input
impedance at 400 Hz is too low.
Figure 9.2b shows a simple means of provided high
CMRR to a resolver-to-digital converter, the input of
which is not well balanced.The unity-gain differential-
input buffers provide balanced, high-impedance inputs,
low output impedance, and excellent long-term gain
accuracy. Offsets are unimportant because the signals
are AC coupled. Note that this aid is not required if the
converter is designed with a proper input circuit.
Let us now consider two input-circuit problems fre-
quently encountered in module or PC board configu-
rations (and other similar high-density system con-
structions), and simple means of preventing them.
One concerns digital-to-analog feedback caused by
common grounds and stray coupling, and the other
concerns pickup of power-supply spikes (and even
VRef
CX
CMV
BALANCED
SCOTT-T
ISOLATION
R/D
CONV.
VRef
TRIPLE TWISTED
(12 TURNS/FT)
SHIELDED INSULATED
CABLE
S/D CONVERTER
DIGITAL
OUTPUT
θ
ELECTROSTATIC
SHIELD GROUNDED
LOCALLY
CONVERTER
GROUND
Vy INPUT
Vx INPUT
R
R
R
R
kR1
kR1
R1
-
+
-
+
-
+
k<<1
SAME CIRCUIT AS ABOVE
Vref
RESOLVER
Figure 9.2a.Ensuring Input Interface Integrity.
Figure 9.2b.Providing very high
CMRR by use of additional circuitry.
(not necessary if converter is well-designed.)
78
TYPICAL APPLICATIONS AND INTERFACE CONSIDERATIONS
R1
R2
S1
S2
S3
R1
R2
S1
S2
S3
AC
REF
AC
REF
0 - 200V
V
V
Figure 9.3.Synchro Zeroing.
Figure 9.3a.
Figure 9.3b.
94
ripple if high-frequency switching regulators are
used) by the input terminals. The solutions involve:
careful isolation of digital and analog grounds and
power-supply returns; guard buses between the
power-supply buses and the signal paths on the PC
card; and the use of wide, low-inductance paths for
grounds to which multiple returns must be made.
Ground-plane (strip-line) techniques, and bypass-
decoupling are sometimes advisable for bringing the
logic-level power supply into the card. Rarely, shield-
ing of the card from the logic-level power-supply bus
may also be necessary.
Trimming and System Setup
Assuming the individual functional modules of a syn-
chro or resolver system have been individually tested
for specified performance before assembly and inter-
connection into a system, the adjustment of the com-
plete system should be an extremely simple matter -
provided that modern, high-performance designs
have been employed. Indeed, by using the best avail-
able converters (which required neither zero-setting
nor gain trimming), the only system adjustments
required are the mechanical nulling of the synchro or
resolver elements (transducers for S/D or R/D sys-
tems and/or receivers for theD/S or D/Rsystems), by
alignment, at appropriate signal conditions.
Synchro Zeroing Procedure
All that is needed to zero a synchro is an AC Voltmeter
with a 200 V scale and a 0.1 V (or less) scale.
Proceed as follows:
1. Set the shaft whose position is being measured
to its zero position.
2. Remove all connections from the synchro and
connect as shown in Figure 9.3a.
3. Unclamp synchro body and rotate until meter
reads a null, then connect meter between S1 and
R2 as shown in Figure 9.3b.
4. If meter reads less than the reference voltage (37
Vrms for 115 Vref), the synchro is at the correct
null and you should proceed to step 5. If the volt-
age is greater than the reference (193 V for 115
Vref), then the synchro body must be rotated 180°
and renulled using the voltmeter as in step 3.
5. Once the correct null position is determined, the
voltmeter should be set successively on lower scales
and the synchro body adjusted for the best null pos-
sible. The synchro is then clamped in position.
If the functional modules used are not permanently
zeroed and/or calibrated, the trimming can be a time-
consuming and tricky procedure, because it is very
often an interactive process ...one in which an adjust-
ment at one point in the system causes a shift in the
adjustment made earlier at another point. Trim proce-
dures, if necessary, should be obtained from the man-
ufacturer, before purchase, to determine the degree of
complexity before a purchase decision is made.
124
SYNCHRO/RESOLVER CARDS
PC-Based Test Cards
Applications using synchro-to-digital (S/D) and
resolver-to-digital (R/D) converters generally require
some form of embedded card test equipment.
Having the ability to simulate and read
synchro/resolver outputs is essential in evaluating
overall system performance. A card-based test
stand offers a low-cost flexible way to handle many of
the testing requirements technicians and engineers
encounter today. Data Device Corporation (DDC)
has a variety of IBM PC-based Synchro/Resolver
cards to accommodate all application or testing
needs.
For low-cost multiple channel applications DDC pro-
vides a full range of component-grade PC ISA-based
cards. Recommended DDC cards for applications
requiring the measurement of position or speed are
listed in Table 10.1.
DDC's SDC-36015 card will provide up to six chan-
nels of synchro/resolver-to-digital conversion. It has
sockets for two families of DDC's popular converters:
the SDC-14560 series and the RDC-19200. For
applications that require 1.3 arc minutes of accuracy
and a synthesized reference, the SDC-14560 series
converters are the ideal choice. The majority of
applications, however, are well-suited for the RDC-
19200 for 2 volt sin/cos or 11.8 volt L-L resolver
applications, or the SDC-19204/6 series of convert-
ers for 11.8 or 90 volt L-L synchro applications.
95
SECTION X
RH
RL
S1
S2
S3
S4
RH
RL
S1
S1
S2
S2
S3
S3
S1
S2
S3
S4
34
1
18
37
19
11
1
18
37
30
19
SDC-36015
SYNCHRO*
RH
RL
S1
S2
S3
S4
11
1
37
19
SDC-36015
DIRECT*
SDC-36015
RESOLVER*
REF IN
GND
REF IN
GND
REF IN
GND
18
COS
SIN
V (DO NOT GROUND)
*TRANSFORMER ISOLATION RECOMMENDED
(with SDC-14560/1/2/3 or
SDC-19204/6 Converters)
(with SDC-14567/8/9 or
RDC-19202 Converters)
(with SDC-14564/5/6 or
RDC-19200 Converters)
Figure 10.1.SDC-36015 Wiring Configurations.
Table 10.1.PC-Based Test Cards
API-36005
SIM-36010
DSC-36022
SDC-36016
DSC-36020
SDC-36015
PART NUMBER
one
one
four
four
six
six
CHANNELS
S/D or R/D
D/S or D/R
D/S or D/R
S/D or R/D
D/S or D/R
S/D or R/D
TYPE
high accuracy
high accuracy
—
—
—
—
SPECIAL FEATURES
148
SYNCHRO/RESOLVER CARDS
These low-cost industrial grade converters are avail-
able in 8, 4, 3 or 2 arc minute accuracy grades. With
the flexibility of programmable resolutions (10-, 12-,
14- or 16-bits) and programmable bandwidth, these
converters can handle a wide variety of applications.
Figure 10.1 shows typical wiring configurations for
the SDC-36015 card.
To provide a lower cost synchro/resolver-to-digital
PC card, Data Device Corporation offers the four-
channel SDC-36016. With a design based on the
RDC-19222 monolithic resolver-to-digital converter,
it provides engineers with the flexibility to measure
position and speed of almost all synchro and resolver
applications. With the ability to program reference
level, bandwidth, and resolution, the SDC-36016
card can interface with applications ranging from a
high-speed motor control feedback to a precision
application requiring 16-bits of resolution. The line-
to line-inputs of the SDC-36016 can be set for 2 volt
sin/cos L-L, 11.8 volt L-L or 90 volt L-L by changing
a thin-film resistor network. The I/O and velocity sig-
nals from these cards are brought off the circuit card
through a 37-pin male "D" type connector mounted
on the rear of the circuit card. See the wiring con-
figurations in Figure 10.2.
For applications where angle simulation is required
there are two component-grade cards available. The
DSC-36020 is a one- to six-channel low-power digi-
tal-to-synchro/resolver PC-based card. It has sock-
ets for three families of DDC's popular converters:
96
RH
RL
S1
S2
S3
S4
RH
RL
S1
S2
S3
34
15
36
17
35
34
15
36
17
18
35
SDC-36016
SYNCHRO
RH
RL
S1
S2
S3
S4
34
15
17
35
SDC-36016
DIRECT
SDC-36016
RESOLVER
(with RDC-19222 and
DDC-49530 or DDC-49590)
(with RDC-19222 and
DDC-55688)
(with RDC-19222 and
DDC-49530)
Figure 10.2.SDC-36016 Wiring Configurations.
RH
RL
S1
S2
S3
RH
RL
S1
S2
S3
RH
RL
S1
S2
S3
RH
RL
S1
S2
S3
17
35
19
37
18
17
35
19
37
18
36
S4
S4
R/D
CONVERTER
S/D
CONVERTER
DSC-36020
CHANNEL1
RESOLVER
DSC-36020
CHANNEL1
SYNCHRO
RH
RL
RH
RL
COS
SIN
COM
COS
SIN
COM
17
35
37
18
36
DIRECT
CONVERTER
DSC-36020
CHANNEL1
DIRECT
(with DSC-11520
or DSC-11524)
(with DSC-11524,
DSC-11520, or
DR-11525)
(with DSC-11524
or DR-11525)
Figure 10.3.DSC-36020 Wiring Configurations.
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