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FEATURES
APPLICATIONS
DESCRIPTION
TPS2220B
SLVS554– JANUARY2005
POWER-INTERFACESWITCHES
FORSERIALPCMCIACONTROLLERS
Power-OnReset
Single-SlotSwitch:TPS2220B
-40°C to85°C OperatingAmbientTemperature
Range
FastCurrentLimitResponseTime
FullyIntegratedVCCandVPPSwitchingfor
3.3V,5V,and12V
NotebookandDesktopComputers
MeetsCurrentPCCard™Standards
BarCodeScanners
V
pp
OutputSelectionIndependentofV
CC
DigitalCameras
12-Vand5-VSuppliesCanBeDisabled
Set-TopBoxes
TTL-LogicCompatibleInputs
PDAs
Short-CircuitandThermalProtection
24-PinHTSSOPand24-PinSSOP
140-µA (Typical)QuiescentCurrentfrom
3.3-VInput
Break-Before-MakeSwitching
The TPS2220B B power-interface e switch provides an integrated power-management t solution for r single Card
sockets.Thedeviceallowsthecontrolleddistributionof3.3V,5V,and12Vtoonecardslot.Thecurrent-limiting
and thermal-protection features eliminate the need for fuses. . Current-limit t reporting g helps s the e user r isolate e a
system fault. The switch r
DS(on)
and current-limit t values s have e been set t for r the peak and average current
requirementsstatedinthePCCardspecification,andoptimizedforcost.
LiketheTPS2220AthisdevicesupportsindependentVPP/VCCswitching.TheTPS2220Bispincompatiblewith
theTPA2220Aexeceptforpin20oftheTPS2220Bwhichhasnoconnection.
AVAILABLEOPTIONS
PACKAGEDDEVICE
PowerPAD™
T
A
PLASTICSMALLOUTLINE
PLASTICSMALLOUTLINE
(DB-24)
(1)
(PWP-24)
(1)
-40°C to85°C
TPS2220BDB
TPS2220BPWP
(1) TheDBandPWPpackagesarealsoavailabletapedandreeled.AddRsuffixtodevicetype(e.g.,TPS2220BPWPR)fortapedand
reeled.
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PowerPADisatrademarkofTexasInstruments.
PCCardisatrademarkofPCMCIA(PersonalComputerMemoryCardInternationalAssociation).
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright©2005,TexasInstrumentsIncorporated
Products conform m to o specifications per the terms of the Texas
Instruments standard d warranty. . Production processing g does s not
necessarilyincludetestingofallparameters.
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ABSOLUTEMAXIMUMRATINGS
DISSIPATIONRATINGTABLE
TPS2220B
SLVS554– JANUARY2005
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedevice
placedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
ORDERINGINFORMATION
T
A
SSOP(DB)
(1)
STATUS
HTSSOP(PWP)
(1)
STATUS
–40°C
to85°C
TPS2220BDB
Active
TPS2220BPWP
Active
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
(1)
TPA2220B
V
I(3.3V)
–0.3 Vto5.5V
V
I
Inputvoltagerangeforcardpower
V
I(5V)
–0.3 Vto5.5V
V
I(12V)
–0.3 Vto14V
Logicinput/outputvoltage
–0.3 Vto6V
V
O(AVCC)
–0.3 Vto6V
V
O
Outputvoltage
V
O(AVPP)
–0.3 Vto14V
Continuoustotalpowerdissipation
SeeDissipationRatingTable
I
O(AVCC)
InternallyLimited
I
O
Outputcurrent
I
O(AVPP)
InternallyLimited
T
J
Operatingvirtualjunctiontemperaturerange
–40°C
to100°C
T
stg
Storagetemperaturerange
–55°C
to150°C
Leadtemperature1,6mm(1/16inch)fromcasefor10seconds)
260°C
OCsinkcurrent
10mA
(1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating
conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
T
A
£25°C
DERATINGFACTOR
T
A
=70°C
T
A
=85°C
PACKAGE
(1)
POWERRATING
ABOVET
A
=25°C
POWERRATING
POWERRATING
DB
24
890mW
8.9mW/°C
489mW
356mW
PWP
24
3322mW
33.22mW/°C
1827mW
1329mW
(1) ThesedevicesaremountedonaaJEDEClow-kboard(2-oz.tracesonsurface).
2
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RECOMMENDEDOPERATINGCONDITIONS
ELECTRICALCHARACTERISTICS
TPS2220B
SLVS554– JANUARY2005
MIN
MAX
UNIT
V
I(3.3V)
(1)
3
3.6
Inputvoltage,V
I(3.3V)
isrequiredforallcircuit
operations.5Vand12Vareonlyrequiredfor
V
I(5V)
3
5.5
V
theirrespectivefunctions.
V
I(12V)
7
13.5
I
O(AVCC)
atT
J
=100°C
1
A
I
O
Outputcurrent
I
O(AVPP)
atT
J
=100°C
100
mA
f
(clock)
Clockfrequency
2.5
MHz
Data
200
Latch
250
t
w
Pulseduration
ns
Clock
100
Reset
100
t
h
Data-to-clockholdtime(seeFigure2)
100
ns
t
su
Data-to-clocksetuptime(seeFigure2)
100
ns
t
d(latch)
Latchdelaytime(seeFigure2)
100
ns
t
d(clock)
Clockdelaytime(seeFigure2)
250
ns
T
J
Operatingvirtualjunctiontemperature(maximumtobecalculatedatworstcaseP
D
at85°C ambient)
–40
100
°C
(1) ItisunderstoodthatforV
I(3.3V)
<3V,voltageswithintheabsolutemaximumratingsappliedtopin5Vorpin12VdonotdamagetheIC.
T
J
=25°C, V
I(5V)
=5V,V
I(3.3V)
=3.3V,V
I(12V)
=12V,alloutputsunloaded(unlessotherwisenoted)
PARAMETER
TESTCONDITIONS
(1)
MIN
TYP
MAX
UNIT
POWERSWITCH
I
O
=750mAeach
85
110
3.3VtoAVCC
I
O
=750mAeach,T
J
=100°C
110
140
mW
I
O
=500mAeach
95
130
5VtoAVCC
I
O
=500mAeach,T
J
=100°C
120
160
Staticdrain-source
r
DS(on)
on-stateresistance
I
O
=50mAeach
0.8
1
3.3Vor5VtoAVPP
I
O
=50mAeach,T
J
=100°C
1
1.3
W
I
O
=50mAeach
2
2.5
12VtoAVPP
I
O
=50mAeach,T
J
=100°C
2.5
3.4
DischargeatAVCC
I
O(disc)
=1mA
0.5
0.7
1
Outputdischarge
kW
resistance
DischargeatAVPP
I
O(disc)
=1mA
0.2
0.4
0.5
I
OS(AVCC)
1
1.4
2
A
Limit(steady-statevalue),output
poweredintoashortcircuit
I
OS(AVPP)
120
200
300
mA
I
OS
Short-circuitoutputcurrent
Limit(steady-statevalue),output
I
OS(AVCC)
1
1.4
2
A
poweredintoashortcircuit,
I
OS(AVPP)
120
200
300
mA
T
J
=100°C
Thermaltrippoint
Risingtemperature
135
Thermalshutdown
T
J
°C
temperature
Hysteresis
10
5VtoAVCC=5V,with100-mWshorttoGND
10
Current-limitresponsetime
(2)(3)
µs
5VtoAVPP=5V,with100-mWshorttoGND
3
I
I(3.3V)
140
200
Normal
V
O
(AVCC)=V
O
(AVPP)=3.3Vand
I
I(5V)
8
12
operation
alsoforRESET=0V
I
I(12V)
100
180
Inputcurrent,quiesc-
I
I
µA
ent
I
I(3.3V)
0.3
2
Shutdownmode
I
I(5V)
V
O
(AVCC)=V
O
(AVPP)=Hi-Z
0.1
2
I
I(12V)
0.3
2
(1) Pulse-testingtechniquesmaintainjunctiontemperatureclosetoambienttemperature;thermaleffectsmustbetakenintoaccount
separately.
(2) Specifiedbydesign;nottestedinproduction.
(3) Fromapplicationofshortto110%offinalcurrentlimit.
3
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TPS2220B
SLVS554– JANUARY2005
ELECTRICALCHARACTERISTICS(continued)
T
J
=25°C, V
I(5V)
=5V,V
I(3.3V)
=3.3V,V
I(12V)
=12V,alloutputsunloaded(unlessotherwisenoted)
PARAMETER
TESTCONDITIONS
(1)
MIN
TYP
MAX
UNIT
10
V
O(AVCC)
=5V,V
I(5V)
=V
I(12V)
=0V
T
J
=100°C
50
Leakagecurrent,
I
lkg
Shutdownmode
µA
outputoffstate
10
V
O(AVPP)
=12V,V
I(5V)
=V
I(12V)
=0V
T
J
=100°C
50
LOGICSECTION(CLOCK,DATA,LATCH,RESET,SHDN,OC)
RESET=5.5V
–1
1
I
I(/RESET)
(4)
RESET=0V
–30
–20
–10
SHDN=5.5V
–1
1
I
I(/SHDN)
(4)
I
I
Inputcurrent,logic
SHDN=0V
–50
-3
µA
LATCH=5.5V
50
I
I(LATCH)
(4)
LATCH=0V
–1
1
I
I(CLOCK, DATA)
0Vto5.5V
–1
1
V
IH
High-levelinputvoltage,logic
2
V
V
IL
Low-levelinputvoltage,logic
0.8
V
V
O(sat)
OutputsaturationvoltageatOC
I
O
=2mA
0.14
0.4
V
I
lkg
LeakagecurrentatOC
V
O(/OC)
=5.5V
0
1
µA
UVLOANDPOR(POWER-ONRESET)
V
I(3.3V)
Inputvoltageat3.3Vpin,UVLO
3.3-VlevelbelowwhichallswitchesareHi-Z
2.4
2.7
2.9
V
V
hys(3.3V)
UVLOhysteresisvoltageatVA
(5)
100
mV
V
I(5V)
Inputvoltageat5Vpin,UVLO
5-Vlevelbelowwhichonly5VswitchesareHi-Z
2.3
2.5
2.8
V
Delayfromvoltagehit(stepfrom3Vto2.3V)to
V
hys(5V)
UVLOhysteresisvoltageat5V
(5)
100
mV
Hi-Zcontrol(90%V
G
toGND)
t
df
Delaytimeforfallingresponse,UVLO
(5)
4
µs
3.3-VvoltagebelowwhichPORisassertedcausinga
V
I(POR)
Inputvoltage,power-onreset
(5)
RESETinternallywithalllineswitchesopenandall
1.7
V
dischargeswitchesclosed.
(4) LATCHhaslow-currentpulldown.RESETandSHDNhavelow-currentpullup.
(5) Specifiedbydesign;nottestedinproduction.
4
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SWITCHINGCHARACTERISTICS
TPS2220B
SLVS554– JANUARY2005
V
CC
=5V,T
A
=25°C, V
I(3.3V)
=3.3V,V
I(5V)
=5V,V
I(12)
=12V,alloutputsunloaded(unlessotherwisenoted)
PARAMETER
(1)
LOADCONDITION
TESTCONDITIONS
(2)
MIN
TYP MAX
UNIT
V
O(AVCC)
=5V
0.9
C
L(AVCC)
=0.1µF, C
L(AVPP)
=0.1µF,
I
O(AVCC)
=0A,I
O(AVPP)
=0A
V
O(AVPP)
=12V
0.26
t
r
Outputrisetimes
(3)
ms
V
O(AVCC)
=5V
1.1
C
L(AVCC)
=150µF, C
L(AVPP)
=10µF,
I
O(AVCC)
=0.75A,I
O(AVPP)
=50mA
V
O(AVPP)
=12V
0.6
V
O(AVCC)
=5V,
0.5
DischargeswitchesON
C
L(AVCC)
=0.1µF, C
L(AVPP)
=0.1µF,
I
O(AVCC)
=0A,I
O(AVPP)
=0A
V
O(AVPP)
=12V,
0.2
t
f
Outputfalltimes
(3)
ms
DischargeswitchesON
V
O(AVCC)
=5V
2.35
C
L(AVCC)
=150µF, C
L(AVPP)
=10µF,
I
O(AVCC)
=0.75A,I
O(AVPP)
=50mA
V
O(AVPP)
=12V
3.9
t
pdon
2
Latch›toAVPP(12V)
t
pdoff
0.62
t
pdon
0.77
Latch›toAVPP(5V)
t
pdoff
0.51
t
pdon
0.75
C
L(AVCC)
=0.1µF, C
L(AVPP)
=0.1µF,
Latch›toAVPP(3.3V)
ms
I
O(AVCC)
=0A,I
O(AVPP)
=0A
t
pdoff
0.52
t
pdon
0.3
Latch›toAVCC(5V)
t
pdoff
2.5
t
pdon
0.3
Latch›toAVCC(3.3V)
t
pdoff
2.8
Propagationdelay
t
pd
times
(3)
t
pdon
2.2
Latch›toAVPP(12V)
t
pdoff
0.8
t
pdon
0.8
Latch›toAVPP(5V)
t
pdoff
0.6
t
pdon
0.8
C
L(AVCC)
=150µF, C
L(AVPP)
=10µF,
Latch›toAVPP(3.3V)
ms
I
O(AVCC)
=0.75A,I
O(AVPP)
=50mA
t
pdoff
0.6
t
pdon
0.6
Latch›toAVCC(5V)
t
pdoff
2.5
t
pdon
0.5
Latch›toAVCC(3.3V)
t
pdoff
2.6
(1) RefertoParameterMeasurementInformationinFigure1.
(2) Nocardinserted,assumesa0.1-µF F outputcapacitor(seeFigure1).
(3) Specifiedbydesign;nottestedinproduction.
5
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See Note A
See Note A
CS
S1
CS
S7
Control Logic
SHDN
RESET
DATA
CLOCK
LATCH
OC
GND
UVLO
POR
Current Limit
Thermal Limit
S2
S3
S4
S5
S6
3.3 V
5 V
5 V
12 V
AVCC
AVCC
AVPP
NOTES:A. Current sense
PIN ASSIGNMENTS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
5
6
7
8
9
10
11
12
TPS2220B
DB OR PWP PACKAGE
(TOP VIEW)
5V
5V
DATA
CLOCK
LATCH
NC
12V
AVPP
AVCC
AVCC
GND
RESET
NC
NC
NC
SHDN
NC
NC
NC
NC
NC
OC
NC
3.3V
NC
No
internal
connection
TPS2220B
SLVS554– JANUARY 2005
FUNCTIONAL BLOCK DIAGRAM
6
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TPS2220B
SLVS554– JANUARY 2005
PIN ASSIGNMENTS (continued)
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
TPS2220B
3.3V
13
I
3.3-V input for card power and chip power
5V
1, 2
I
5-V input for card power
12V
7
I
12-V input for card power (AVPP).
AVCC
9, 10
O
Switched output that delivers 3.3 V, 5 V, ground or high impedance to card
AVPP
8
O
Switched output that delivers 3.3 V, 5 V, 12 V, ground or high impedance to card
GND
11
Ground
Open-drain overcurrent reporting output that goes low when an overcurrent condition exists. An external
OC
15
O
pullup is required.
Hi-Z (open) all switches. Identical function to serial D8. Asynchronous active-low command, internal
SHDN
21
I
pullup
RESET
12
I
Logic-level RESET input active low. Asynchronous active-low command, internal pullup
CLOCK
4
I
Logic-level clock for serial data word
DATA
3
I
Logic-level serial data word
LATCH
5
I
Logic-level latch for serial data word, internal pulldown
6, 14, 16,
17, 18, 19,
NC
No internal connection
20, 22, 23,
24
7
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PARAMETER MEASUREMENT INFORMATION
50%
LATCH
V
DD
GND
10%
90%
t
pd(on)
GND
V
O(AVPP)
Propagation Delay (AVPP)
50%
LATCH
V
DD
GND
10%
90%
t
pd(on)
GND
V
O(AVCC)
Propagation Delay (AVCC)
10%
90%
t
r
GND
V
O(AVPP)
Rise/Fall Time (AVPP)
t
f
10%
90%
t
r
GND
V
O(AVCC)
Rise/Fall Time (AVCC)
t
f
50%
V
DD
GND
10%
90%
t
on
GND
V
O(AVCC)
Turnon/off Time (AVCC)
AVPP
VOLTAGE WAVEFORMS
LOAD CIRCUIT (AVPP)
I
O(AVPP)
AVCC
50%
LATCH
V
DD
GND
10%
90%
t
on
GND
V
O(AVPP)
Turnon/off Time (AVPP)
I
O(AVCC)
t
pd(off)
t
pd(off)
t
off
t
off
LOAD CIRCUIT (AVCC)
V
I(12V/5V/3.3V)
V
I(5V/3.3V)
V
I(12V/5V/3.3V)
V
I(5V/3.3V)
V
I(12V/5V/3.3V)
V
I(5V/3.3V)
LATCH
D10
D9
D8
D7
D6
D5
D4
D3
D2
DATA
LATCH
CLOCK
D1
D0
Data Setup Time
Data Hold Time
Latch Delay Time
Clock Delay Time
TPS2220B
SLVS554– JANUARY 2005
Figure 1. Test Circuits and Voltage Waveforms
NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next
positive edge of the clock. For definition of D0 to D10, see the control logic table.
Figure 2. Serial-Interface Timing for TPS2220B
8
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Table of Graphs
TPS2220B
SLVS554– JANUARY 2005
FIGURE
Short-circuit response, short applied to powered-on 5-V AVCC-switch output
vs Time
3
Short-circuit response, short applied to powered-on 12-V AVPP-switch output
vs Time
4
OC response with ramped overcurrent-limit load on 5-V AVCC-switch output
vs Time
5
OC response with ramped overcurrent-limit load on 12-V AVPP-switch output
vs Time
6
AVCC Turnon propagation delay time (C
L
=150 µF)
vs Junction temperature
7
AVCC Turnoff propagation delay time (C
L
=150 µF)
vs Junction temperature
8
AVPP Turnon propagation delay time (C
L
=10 µF)
vs Junction temperature
9
AVPP Turnoff propagation delay time (C
L
=10 µF)
vs Junction temperature
10
AVCC Turnon propagation delay time (T
J
=25°C)
vs Load capacitance
11
AVCC Turnoff propagation delay time (T
J
=25°C)
vs Load capacitance
12
AVPP Turnon propagation delay time (T
J
=25°C)
vs Load capacitance
13
AVPP Turnoff propagation delay time (T
J
=25°C)
vs Load capacitance
14
AVCC Rise time (C
L
=150 µF)
vs Junction temperature
15
AVCC Fall time (C
L
=150 µF)
vs Junction temperature
16
AVPP Rise time (C
L
=10 µF)
vs Junction temperature
17
AVPP Fall time (C
L
=10 µF)
vs Junction temperature
18
AVCC Rise time (T
J
=25°C)
vs Load capacitance
19
AVCC Fall time (T
J
=25°C)
vs Load capacitance
20
AVPP Rise time (T
J
=25°C)
vs Load capacitance
21
AVPP Fall time (T
J
=25°C)
vs Load capacitance
22
9
www.ti.com
1
2
3
4
5
t − Time − ms
0
V
O(/OC)
2 V/div
I
O(xVPP)
2 A/div
100
200
300
400
500
t − Time − ms
0
V
O(/OC)
5 V/div
I
O(VCC)
5 A/div
V
IN(5V)
2 V/div
10
20
30
40
50
t − Time − ms
0
V
O(/OC)
5 V/div
I
O(xVCC)
1 A/div
2
4
6
8
10
t − Time − ms
0
V
O(/OC)
5 V/div
I
O(xVPP)
100 mA/div
TPS2220B
SLVS554– JANUARY 2005
SHORT-CIRCIUT RESPONSE,
SHORT-CIRCIUT RESPONSE,
SHORT APPLIED TO POWERED-ON 5-V
SHORT APPLIED TO POWERED-ON 12-V
AVCC-SWITCH OUTPUT
AVPP-SWITCH OUTPUT
Figure 3.
Figure 4.
OC RESPONSE WITH RAMPED
OC RESPONSE WITH RAMPED
OVERCURRENT-LIMIT LOAD ON 5-V
OVERCURRENT-LIMIT LOAD ON 12-V
AVCC-SWITCH OUTPUT
AVPP-SWITCH OUTPUT
Figure 5.
Figure 6.
10
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