51
R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
336
NTR bit =0: the EVENt bit is not set.
This part can be overwritten and read at will. Reading the PTRansition register is nondestructive.
EVENt
The EVENt part indicates whether an event has occurred since the last reading, it is the "memory"
of the condition part. It only indicates events passed on by the transition filters. It is permanently
updated by the instrument. This part can only be read by the user. Reading the register clears it.
This part is often equated with the entire register.
ENABle
The ENABle part determines whether the associated EVENt bit contributes to the sum bit (cf.
below). Each bit of the EVENt part is ANDed with the associated ENABle bit (symbol '&'). The
results of all logical operations of this part are passed on to the sum bit via an OR function
(symbol '+').
ENAB bit =0: The associated EVENt bit does not contribute to the sum bit.
ENAB bit =1: If the associated EVENT bit is "1", the sum bit is set to "1" as well.
This part can be overwritten and read by the user at will. Its contents are not affected by reading.
As shown in the graphical overview, the status information is of hierarchical structure.
STB, SRE The register STatus Byte (STB) defined in IEEE 488.2 and its associated mask register
Service Request Enable (SRE) form the highest level of the status reporting system. The STB
provides a rough overview of the instrument status, collecting the information of the lower-level
registers.
ESR, SCPI registers
The STB receives its information from the following registers:
The standard IEEE 488.2 Event Status Register (ESR) with the associated mask register
standard event status enable (ESE).
The STATus:OPERation and STATus:QUEStionable registers which are defined by SCPI
and contain detailed information on the instrument.
IST, PPE The IST flag ("Individual STatus"), like the SRQ, combines the entire instrument status in
asingle bit. The PPE is associated to the IST flag. It fulfills an analogous function for the IST flag
as the SRE does for the service request.
Output buffer contains the messages the instrument returns to the controller. It is not part of the
status reporting system but determines the value of the MAV bit in the STB and thus is
represented in the overview.
The sum bit is obtained from the EVENt and ENABle part for each register. The result is then entered into
abit of the CONDition part of the higher-order register.
The instrument automatically generates the sum bit for each register. Thus an event can lead to a service
request throughout all levels of the hierarchy.
C# HTML5 Viewer: Deployment on ASP.NET MVC Right-click Home and select "Add New Item", pop-up box as follows, select MVC 3 View Page (ASPX) and rename it. RasterEdge.XDoc.PDF.dll.
remove metadata from pdf acrobat; batch pdf metadata
46
R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
337
Status Registers
Contents of the Status Registers
The individual status registers are used to report different classes of instrument states or errors. The
following status registers belong to the general model described in IEEE 488.2:
The STatus Byte (STB) gives a rough overview of the instrument status.
The IST flag combines the entire status information into a single bit that can be queried in a
parallel poll.
The Event Status Register (ESR) indicates general instrument states.
The status registers below belong to the device-dependent SCPI register model:
The STATus:OPERation register contains conditions which are part of the instrument's normal
operation.
The STATus:QUEStionable register indicates whether the data currently being acquired is of
questionable quality.
The STATus:QUEStionable:LIMit<1|2> register indicates the result of the limit check.
STB and SRE
The STatus Byte (STB) provides a rough overview of the instrument status by collecting the pieces of
information of the lower registers. The STB represents the highest level within the SCPI hierarchy. A
special feature is that bit 6 acts as the summary bit of the remaining bits of the status byte.
SRE and Service Request
The STatus Byte (STB) is linked to the Service Request Enable (SRE) register on a bit-by-bit basis.
The STB corresponds to the CONDition part of an SCPI register, indicating the current instrument
state.
The SRE corresponds to the ENABle part of an SCPI register.If a bit is set in the SRE and the
associated bit in the STB changes from 0 to 1, a Service Request (SRQ) is generated on the
GPIB bus.
Bit 6 of the SRE is ignored, because it corresponds to the summary bit of the STB.
Related common commands
The STB is read out using the command *STB? or a serial poll.
The SRE can be set using command *SRE and read using *SRE?.
The bits in the STB are defined as follows:
Bit
No.
Meaning
43
R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
338
3
QUEStionable status summary bit
This bit is set if an EVENt bit is set in the QUEStionable register and the associated ENABle bit is set to
1.
The bit indicates a questionable instrument status, which can be further pinned down by polling the
QUEStionable register.
5
ESB bit
Sum bit of the event status register. It is set if one of the bits in the event status register is set and
enabled in the event status enable register.
Setting of this bit implies an error or an event which can be further pinned down by polling the event
status register.
IST Flag and PPE
In analogy to the Service Request (SRQ), the IST flag combines the entire status information in a single
bit. It can be queried by means of a parallel poll.
The Parallel Poll Enable (PPE) register determines which bits of the STB contribute to the IST flag. The
bits of the STB are ANDed with the corresponding bits of the PPE, with bit 6 being used as well in contrast
to the SRE. The IST flag results from the ORing of all results.
Related common commands
The IST flag is queried using the command *IST?.
The PPE can be set using *PRE and read using command *PRE?.
ESR and ESE
The Event Status Register (ESR) indicates general instrument states. It is linked to the Event Status
Enable (ESE) register on a bit-by-bit basis.
The ESR corresponds to the CONDition part of an SCPI register, indicating the current instrument
state.
The ESE corresponds to the ENABle part of an SCPI register. If a bit is set in the ESE and the
associated bit in the ESR changes from 0 to 1, the ESB bit in the STatus Byte is set.
Related common commands
The Event Status Register (ESR) can be queried using ESR?.
The Event Status Enable (ESE) register can be set using the command *ESE and read using *ESE?.
The bits in the ESR are defined as follows:
Bit No. Meaning
0
Operation Complete
This bit is set on receipt of the command *OPC after all previous commands have been executed.
53
R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
339
STATus:OPERation
The STATus:OPERation register contains conditions which are part of the instrument's normal operation.
The analyzer does not use the STATus:OPERation register:
STATus:QUEStionable
The STATus:QUEStionable register indicates whether the acquired data is of questionable quality and
monitors hardware failures of the analyzer. It can be queried using the commands
STATus:QUEStionable:CONDition? or STATus:QUEStionable[:EVENt]?
The bits in the STATus:QUEStionable register are defined as follows:
Bit
No.
Meaning
9
Integrity Register summary
This bit is set if a bit is set in the STATus:QUEStionable:INTegrity register and the associated ENABle
bit is set to 1.
10
Limit Register summary
This bit is set if a bit is set in the STATus:QUEStionable:LIMit1 register and the associated ENABle bit is
set to 1.
STATus:QUEStionable:LIMit1<1|2>
The STATus:QUEStionable:LIMit<1|2> registers indicate the result of the limit check. They can be queried
using the commands STATus:QUEStionable:LIMit<1|2>:CONDition? or
STATus:QUEStionable:LIMit<1|2>[:EVENt]? STATus:QUEStionable:LIMit1 is also the summary
register of the lower-level STATus:QUEStionable:LIMit2 register.
The bits in the STATus:QUEStionable:LIMit1 register are defined as follows:
Bit
No.
Meaning
0
LIMit2 Register summary
This bit is set if a bit is set in the STATus:QUEStionable:LIMit2 register and the associated ENABle bit
is set to 1.
1
Failed Limit Check for Trace no. 1
This bit is set if any point on trace no. 1 fails the limit check.
...
...
14
Failed Limit Check for Trace no. 14
This bit is set if any point on trace no. 14 fails the limit check.
The bits in the STATus:QUEStionable:LIMit2 register are defined as follows:
Bit No.
Meaning
0
Not used
1
Failed Limit Check for Trace no. 15
This bit is set if any point on trace no. 15 fails the limit check.
53
R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
340
2
Failed Limit Check for Trace no. 16
This bit is set if any point on trace no. 16 fails the limit check.
Numbering of traces
The traces numbers 1 to 16 are assigned as follows:
Traces assigned to channels with smaller channel numbers have smaller trace numbers.
Within a channel, the order of traces reflects their creation time: The oldest trace has the smallest,
the newest trace has the largest trace number. This is equivalent to the order of traces in the
response string of the CALCulate<Ch>:PARameter:CATalog? query.
The number of traces monitored cannot exceed 16. If a setup contains more traces, the newest
traces are not monitored.
STATus:QUEStionable:INTegrity...
The STATus:QUEStionable:INTegrity register monitors hardware failures of the analyzer. It can be
queried using the commands STATus:QUEStionable:INTegrity:CONDition? or
STATus:QUEStionable:INTegrity[:EVENt]? STATus:QUEStionable:INTegrity is also the summary
register of the lower-level STATus:QUEStionable:INTegrity:HARDware register.
Refer to the Error Messages section for a detailed description of hardware errors including possible
remedies.
The bits in the STATus:QUEStionable:INTegrity register are defined as follows:
Bit
No.
Meaning
2
HARDware Register summary
This bit is set if a bit is set in the STATus:QUEStionable:INTegrity:HARDware register and the
associated ENABle bit is set to 1.
The STATus:QUEStionable:INTegrity:HARDware register can be queried using the commands
STATus:QUEStionable:INTegrity:HARDware:CONDition? or
STATus:QUEStionable:INTegrity:HARDware[:EVENt]?
The bits in the STATus:QUEStionable:INTegrity:HARDware register are defined as follows:
Bit
No.
Meaning
0
Not used
1
ExtRef unlock
With external reference signal (System – External Reference active) or option ZVAB-B4 (oven quartz),
the reference oscillator is phase locked to a 10 MHz signal. This bit is set if this phase locked loop (PLL)
fails.
For external reference: check frequency and level of the supplied reference signal.
3
Receiver overload
This bit is set if the analyzer detects an excessive input level at one of the ports.
Reduce RF input level at the port. Check amplifiers in the external test setup.
52
R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
341
4
IF overload
The internal local oscillator (LO) signal is phase locked to a 10 MHz signal. This message appears
when the internal phase locked loop (PLL) fails.
Reduce RF input level at the port. Check amplifiers in the external test setup.
5
LO unlocked
This bit is set if the analyzer detects that the instrument temperature is too high.
Shut down and restart the analyzer.
8
OCXO oven cold
This bit is set if the oven for the optional oven quartz (OCXO, option FSL-B4) is not at its operating
temperature.
Wait until the oven has been heated up.
9...
Not used
Application of the Status Reporting System
The purpose of the status reporting system is to monitor the status of one or several devices in a
measuring system. To do this and react appropriately, the controller must receive and evaluate the
information of all devices. The following standard methods are used:
Service request (SRQ) initiated by the measuring device
Serial poll of all devices in the bus system, initiated by the controller in order to find out who sent a
SRQ and why
Parallel poll of all devices
Query of a specific instrument status by means of commands
Query of the error queue
Service Request
The measuring device can send a service request (SRQ) to the controller. Usually this service request
causes an interrupt, to which the control program can react appropriately.
Initiating an SRQ
As shown in the graphical overview, an SRQ is initiated if one or several of bits 2, 3, 4, 5 or 7 of the status
byte are set and enabled in the SRE. Each of these bits summarizes the information of a further register,
the error queue or the output buffer.
The ENABle parts of the status registers can be set such that arbitrary bits in an arbitrary status register
initiate an SRQ. To use the possibilities of the service request effectively, all bits in the enable registers
SRE and ESE should be set to "1".
Examples:
Use *OPC to generate an SRQ
1. Set bit 0 in the ESE (Operation Complete).
2. Set bit 5 in the SRE (ESB).
3. Insert *OPC in the command sequence (e.g. at the end of a sweep).
40
R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
342
As soon as all commands preceding *OPC have been completed, the instrument generates an
SRQ.
Generate an SRQ when a limit is exceeded
1. Set bit 3 in the SRE (summary bit of the STATus:QUEStionable register, set after
STATus:PRESet)
2. Set bit 10 in the STATus:QUEStionable:ENABle register (summary bit of the
STATus:QUEStionable:LIMit1 register)
3. Set bit 1 in the STATus:QUEStionable:LIMit1:ENABle register
The analyzer generates a SRQ when the event associated with bit 1 of the
STATus:QUEStionable:LIMit1:ENABle register occurs, i.e. when any point on the first trace fails
the limit check.
Find out which event caused an SRQ
The procedure to find out which event caused an SRQ is analogous to the procedure to generate
an SRQ:
1. STB? (query the contents of the status byte in decimal form)
If bit 3 (QUEStionable summary bit) is set, then:
2. STAT:QUES:EVENT? (query STATus:QUEStionable register)
If bit 10 (QUEStionable:LIMit1 summary bit) is set, then:
3. Query STAT:QUES:LIMit1:EVENT? (query STATus:QUEStionable:LIMit1 register)
If bit 1 is set, then the first trace failed the limit check.
The SRQ is the only possibility for the instrument to become active on its own. Each
controller program should set the instrument such that a service request is initiated in the
case of malfunction. The program should react appropriately to the service request.
Serial Poll
In a serial poll, the controller queries the STatus Bytes of the devices in the bus system one after another.
The query is made via interface messages, so it is faster than a poll by means of *STB?.
Serial poll procedure
The serial poll method is defined in IEEE 488.1 and used to be the only standard possibility for different
instruments to poll the status byte. The method also works for instruments which do not adhere to SCPI or
IEEE 488.2.
The Visual BASIC command for executing a serial poll is "IBRSP()".
The serial poll is mainly used to obtain a fast overview of the state of several instruments connected to the
controller.
57
R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
343
Parallel Poll
In a parallel poll, up to eight instruments are simultaneously requested by the controller by means of a
single command to transmit 1 bit of information each on the data lines, i.e., to set the data line allocated to
each instrument to a logical "0" or "1".
Parallel poll procedure
In addition to the SRE register, which determines the conditions under which an SRQ is generated, there
is a Parallel Poll Enable register (PPE) which is ANDed with the STB bit by bit, considering bit 6 – AND as
well. This register is ANDed with the STB bit by bit, considering bit 6 as well. The results are ORed, the
result is possibly inverted and then sent as a response to the parallel poll of the controller. The result can
also be queried without parallel poll by means of the command "*IST?".
The instrument first has to be set for the parallel poll using the Visual BASIC command "IBPPC()". This
command allocates a data line to the instrument and determines whether the response is to be inverted.
The parallel poll itself is executed using "IBRPP()".
The parallel poll method is mainly used to find out quickly which one of the instruments connected to the
controller has sent a service request. To this effect, SRE and PPE must be set to the same value.
Query of an Instrument Status
Each part of any status register can be read by means of queries. There are two types of commands:
The common commands *ESR?, *IDN?, *IST?, *STB? query the higher-level registers.
The commands of the STATus system query the SCPI registers (STATus:QUEStionable...)
All queries return a decimal number which represents the bit pattern of the status register. This number is
evaluated by the controller program.
Decimal representation of a bit pattern
The STB and ESR registers contain 8 bits, the SCPI registers 16 bits. The contents of a status register is
keyed and transferred as a single decimal number. To make this possible, each bit is assigned a weighted
value. The decimal number is calculated as the sum of the weighted values of all bits in the register that
are set to 1.
Bits
Weight
0
1
2
3
4
5
6
7
...
1
2
4
8
16
32
64
128
...
Example: The decimal value 40 = 32 + 8 indicates that bits no. 3 and 5 in the status register (e.g. the
QUEStionable status summary bit and the ESB bit in the STatus Byte) are set.
Queries are usually used after an SRQ in order to obtain more detailed information on the cause of the
SRQ.
76
R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
344
Error Queue
Each error state in the instrument leads to an entry in the error queue. The entries of the error queue are
detailed plain text error messages that can be looked up in the Error Log or queried via remote control
using SYSTem:ERRor[:NEXT]? or SYSTem:ERRor:ALL?. Each call of SYSTem:ERRor[:NEXT]?
provides one entry from the error queue. If no error messages are stored there any more, the instrument
responds with 0, "No error".
The error queue should be queried after every SRQ in the controller program as the entries describe the
cause of an error more precisely than the status registers. Especially in the test phase of a controller
program the error queue should be queried regularly since faulty commands from the controller to the
instrument are recorded there as well.
Reset Values of the Status Reporting System
The table below indicates the effects of various commands upon the status reporting system of the
analyzer.
Event
Switching
on
supply
voltage
Power-On-
Status-Clear
DCL,SDC(Device
Clear,
Selected Device
Clear)
*RST or
SYSTem:PRESet
STATus:PRESet *CLS
Effect
0
1
Clear STB,ESR
yes
yes
Clear SRE,ESE
yes
Clear PPE
yes
Clear EVENt parts of the
registers
yes
yes
Clear ENABle parts of all
OPERation-and
QUESTionable registers,
Fill ENABle parts of all
other registers with "1".
yes
yes
Fill PTRansition parts
with „1"
Clear NTRansition parts
yes
yes
Clear error queue
yes
yes
yes
Clear output buffer
yes
yes
yes
1)
1)
1)
Clear command
processing and input
buffer
yes yes
yes
1) Every command being the first in a command line, i.e. immediately following a <PROGRAM MESSAGE TERMINATOR> clears
the output buffer.
Documents you may be interested
Documents you may be interested
