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FUNDAMENTALS

wave is exactly equal to (θ−α). If α, the time-phase

error caused by rotor-to-stator phase lead, is small

compared to θ, the time interval (t

) between the zero

crossings of V

and V

ref

is a measure of θ. In Figure

1.22, a counter totals the number digital clock pulse

during the time interval t

, and the clock frequency is

scaled appropriately, to make the count read directly

in digitally coded angle.

It is readily apparent that the only advantage of the

single-RC S/D or R/D converter is its simplicity. The

disadvantages of this approach are:

• The difficulty of maintaining ωRC=1 due to instabil-

ity in the capacitor with time and temperature.

• The difficulty of maintaining ωRC=1 due to varia-

tions in the carrier frequency. (These may be

eliminated, at

considerable

expense, by

generat-

ing

the carrier in the converter, preferably by divid-

ing down from the clock frequency.)

• The difficulty of maintaining negligible time-phase

error (α) in the reference wave. (Some relief is

obtained by compensating the reference input by

using a lag network, but αvaries with temperature,

θ, excitation, and from synchro to synchro.)

• Significant error due to noise, quadrature compo-

nents in V

and V

, and harmonics in V

and V

particularly around the zero (θ = 0°) and full scale

(θ = 360°).

•

Staleness error

, due to the fact that only one con-

version is made per cycle.

• The circuit will only work at

one specific carrier fre-

quency

The above list confines the single-RC phase-shift

converter to relatively low accuracy applications.

The double-RC phase-shift synchro-to-digital

converter shown in Figure 1.23 eliminates at least

two of the error sources that limit the performance of

the single-RC converter.In this approach, V

and V

have equal but opposite phase shifts with respect to

ref

. By measuring the time interval (t

2θ

) between

the zero crossing of V

and V

, and using it to gate

a clock pulse into the counter, the count may be

scaled to read directly in degrees of θ (i.e., at one-

half the clock-pulse frequency used in the single-RC

design). The disadvantages of this approach are the

same as those listed for the single-RC approach,

with the following exceptions:

•

The time-phaseerror (α) in the V

ref

is no longer an

error factor.

•

The reference carrier frequency need not be quite

as stable as before, but it is still a major error fac-

tor, and must still be internally generated, for even

moderate accuracy.

•

There is a partial improvement in effective RC sta-

bility, due to the tendency of the capacitors to track

each other with temperature.

•

There is an

added

difficulty in the double-RC

approach - a 180° anomaly that causes the same

reading at θand θ±180°. This requires special cir-

cuitry to prevent false readings.

All other error factors remain the same;nevertheless,

at considerable expense, the double-RC phase-shift

S/D or R/D converter can be made to perform at

moderate accuracies ...of the order of a worst-case

limit of errorof 10 minutes.

The real-time trigonometric function-generator

approach of Figure 1.24 takes many forms - one of

which, and perhaps the most advanced, is analyzed

in great detail in Section V. In this generalized dis-

cussion, however, we shall categorize it as follows:

the resolver-format signals V

and V

are applied to

trigonometric function generators (tangent bridges or

sine/cosine non-linear multipliers) and, by manipulat-

ing the resultant generator outputs in accordance

with trigonometric identities, an analog voltage pro-

portional to the difference between θ and the func-

tion-generator setting φ is developed. If the integral

of this voltage is digitized, and the digital value fed

back, as φ, to program the bridge so as to drive (θ-

φ) to null zero, the digital value of φ will equal the

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FUNDAMENTALS

shaft angleθ. This scheme has the following advan-

tages over the two preceding approaches:

•

It is a real-time, continuous measurement of θ;

hence, there is no staleness error.

•

It is inherently a

ratio

technique (V

) - always

an advantage in maintaining accuracy.

•

It is independent of the carrier frequency - indeed

it is broadband, and will work over several

decades of frequency, without special designs.

•

It makes it possible to reject quadrature compo-

nents.

•

It makes it possible to reject most noise compo-

nents.

•

It rejects most harmonic distortion, being responsive

only to differential harmonics between V

and V

•

It is relatively independent of reference time-phase

error, α.

•

There is no 180° anomaly.

Implementation of the real-time function-generator

approach was more expensive than either of the

foregoing schemes, but mass-production techniques

and integrated circuits have erased the cost differ-

ences. The real-time function-generator approach

can achieve state-of-the-art performance - accura-

cies better than ±2 seconds.

Now, let us consider an approach that has some of

the advantages of Figure 1.24 but also a few disad-

vantages. In the past it offered a good price perfor-

mance compromise but with the recent introduction

of monolithic R/Ds it is no longer a viable approach

for new designs. It is discussed here only for histor-

ical purposes. This approach is called the ratio-

boundedharmonic oscillatorcircuitand is shown

in Figure 1.25. (This approach is analyzed in great

detail on pages 29 to 30.) In this technique, a pair of

integrators are cascaded with a unity-gain inverter,

into a closed loop with positive feedback, so that

they will oscillate a frequency determined by their

RC time constants. (Note that the oscillation fre-

quency need have no special relationship to the ref-

erence carrier frequency, except that it is usually

high, for conversion speed.) First, the integrators are

“bound” (i.e., presented with initial conditions) by

presetting their output voltages in the ratio V

These voltages are obtained by simultaneous sam-

pling of V

and V

.Then, the loop is allowed to oscil-

late, and the ratio of the time interval between the

zero crossing of the signal at B in the positive going

direction to the total natural period of oscillation is

exactly proportional to θ. This ratio is digitized by

counting clock pulses, as in earlier schemes.

Indeed, the circuit of Figure 1.25 has some signifi-

cant disadvantages: It is

not

a real-time measure-

ment, but is, instead, a periodic technique, like the

phase-shift converters, and therefore suffers from

staleness error and is costly to produce compared to

modern tracking S/D or R/D designs.

The Demodulation,A/D,and µP approachto syn-

chro/resolver conversionhas been used from time

to time but is now seldom used for new designs

because it burdens the µP, has significant staleness

errors, is susceptible to noise and cannot respond

adequately in a dynamic environment.

In this approach, shown in Figure 1.26, the sine and

cosine analog data is demodulated with the reference

to obtain DC sine and DC cosine. These are then

multiplexed into an A/D converter. The two data words

are then fed to the µP which determines the angle.

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THEORY OF OPERATION OF MODERN

S/D AND R/D CONVERTERS

SECTION II

Figure 2.1.Block Diagram - Synchro-to-Digital Converter

The Tracking Converter

Figure 2.1 is a functional block diagram of a 16-bit

synchro-to-digital tracking converter. Three-wire

synchro angle data are presented to a solid-state

Scott-T (see page 6) which translates them into two

signals, the amplitude of one being proportional to

the sine of θ (the angle to be digitized), and the

amplitude of the other being proportional to the

cosine of θ. (The amplitudes referred to are, of

course, the carrier amplitudes at the reference fre-

quency - i.e., the cosine wave is actually cosθcosωt,

but the carrier term cosωt will be ignored in this dis-

cussion, because it will be removed in the demodu-

lator and, in theory, contains no data.)

A quadrant selector circuit contained in the control

transformer enables selection of the quadrant in

which θ lies, and automatically sets the polarities of

the sinθand cosθsignals appropriately, for computa-

tional significance. The sinθ, cosθ outputs of the

quadrant selector are then fed to the sine and cosine

multipliers, also contained in the control transformer.

These multipliers are digitally programmed resistive

networks. The transfer function of each of these net-

works is determined by a digital input (which switch-

es in proportioned resistors), so that the instanta-

neous value of the output is the productof the instan-

taneous value of the analog input and the sine (or

cosine) of the digitally encoded angle φ. If the instan-

taneous value of the analog input to the sine multi-

plier is cosθ, and digitally encoded "word" presented

to the sine multiplier is φ, then the output is cosθsinφ.

CONTROL

TRANSFORMER

DATA

LATCH

GAIN

DEMODULATOR

16-BIT

UP/DOWN

COUNTER

HYSTERESIS

+REF -REF

BIT

VCO

TIMING

INH

EM DATA EL

INTEGRATOR

VEL

INPUT OPTION

LOS

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Thus the two outputs of the multipliers are:

from the sine multiplier, cosθsinφ

from the cosine multiplier sinθcosφ

These outputs are fed to an operational subtractor, at

the differencing junction shown, so that the input fed

to the demodulator is:

sinθ cosφ – cosθ sinφ=sin(θ-φ)

The right-hand side of this trigonometric identity indi-

cates that the differencing-junction output represents

a carrier-frequency sine wave with an amplitude pro-

portional to the sine of the difference between θ(the

angle to be digitized) and φ(the angle stored in digi-

tal form in the up-down counter). This point is AC

error and is sometimes brought out of the converter

as "e."

The demodulator is also presented with the refer-

ence voltage, which has been isolated from the ref-

erence source and appropriately scaled by the refer-

ence isolation transformer or buffer. The output of

the demodulator is, then, an analog DC level, pro-

portional to:sin (

–

). In other words, the output of

the demodulator is the sine of the "error" between

the actual angular position of the synchro or resolver,

and the digitally encoded angle, θ, which is the out-

put of the counter. This point, the DC error, is also

sometimes brought out as "D" while the addition of a

threshold detector will give a Built-In-Test (BIT) flag.

Note that, for small errors, sin (error) ≅ (error). This

analog error signal is then fed to the circuit block

labeled "error processorand VCO." This circuit con-

sists essentially of an analog integratorwhose output

(the time-integral of the error) controls the frequency

of a voltage-controlled oscillator (VCO). The VCO

produces "clock" pulses that are counted by the up-

down counter. The "sense" of the error (φtoo high or

φtoo low) is determined by the polarity of φ, and is

used to generate a counter control signal "U," which

determines whether the counter increments upward

or downward, with each successive clock pulse fed

to it. (For reasons discussed below, it is also conve-

nient to put a small "hysteresis" into the reaction of

this error processor.) This direction line, (U), can be

used to tell the system which direction the synchro or

resolver is moving. The "clock" or "toggle" line is

brought out as the converter busy (CB) signal. The

carry signal of the last stage of the counter can be

used as a major carry (MC) in multiturn applications.

Note that the two most significant bits of the angle φ,

stored in the up-down counter, are used to control

quadrant selection (as explained on pages 9 and

47), and the remaining 14 bits are fed (in parallel) to

the digital inputs of both multipliers. (It is also inter-

esting to note that the fact that the first two bits of φ

have been "stripped off," for quadrant selection does

not invalidate the explanations given above since

their data merely represent four sets of data from

zero in 90° increments added to the sine/cosine cal-

culations of the function generators, which are strict-

ly one-quadrant full-scale devices).

Finally, note that the up-down counter, like any

counter, is functionally an integrator- an incremental

integrator, but nevertheless an integrator. Therefore,

the tracking converter constitutes in itself a closed-

loop servomechanism (continuously attempting to

nullthe error to zero) with two lags ...two integrators

in series. This is called a "Type II" servo loop, which

has very decided advantages over Type I or Type 0

loops, as we shall see.

To appreciate the value of the Type II servo behavior

of this tracking converter, consider first that the shaft

of the synchro or resolver is not moving. Ignoring

inaccuracies, drifts, and the inevitable quantizing

error (e.g., ±1/2 LSB), the error should be zero

(θ = φ), and the digital output represents the true

shaft angle of the synchro or resolver.

Now, start the synchro or resolver shaft moving, and

allow it to accelerate uniformly, from dθ/dt = 0 to

dθ/dt = V. During the acceleration, an error will

develop, because the converter cannot instanta-

neously respond to the change of angular velocity.

However, since the VCOis controlled by an integra-

tor, the output of which is the integral of the error, the

greater the lag (between θand φ), the faster will the

counter be called upon to "catch up." So when the

THEORY OF OPERATION OF MODERN

S/D AND R/D CONVERTERS

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velocity becomes constant at V, the VCO will have

settled to a ratio of counting that exactly corresponds

to the rate of change in θ per unit time and instanta-

neously θ= φ.This means that dφ/dt will always equal

("track") dφ/dt without a velocityor position error. The

only errors, therefore, will be momentary (transient)

errors, during acceleration or deceleration.

Furthermore, the information produced by the track-

ing converter is always "fresh," being continually

updated, and always available, at the output of the

counter. Since dθ/dt tracks the input velocity it can

be brought out as a velocity (VEL) or tracking rate

signal which is of sufficient linearity in modern con-

verters to eliminate the need for a tachometer (tach-

o-generator) in many systems. Suitably scaled it can

be used as the velocity feedback signal to stabilize

the servo system or motor. A further discussion of

dynamic errors can be found in Section VII.

In older designs, use of the inhibit (INH) command

would lock the converter counter while data was trans-

ferred. This could introduce errors if the INH was

applied too long. If the counter was frozen for more

than a few updates the catch up or reacquisition time

could be significant. Modern designs now use latched

and buffered output configurations which eliminate

this problem and greatly simplify the interface.

Two additional features of this converter should be

mentioned before concluding this description. One

concerns the fact that the velocity range over which

the device will track perfectly (i.e., over which the

velocity errorwill be zero) is determined primarily by

the upper frequency limit of the VCO/counter combi-

nation. A typical high-performance 14-bit, 400 Hz

converter will track at 12 RPS (by no means the limit

of current technology), which corresponds to 12 x 2

counts/sec, or 196,608 counts/sec.

The other feature is indirectly related to tracking rate

also. To optimize recovery from velocity changes

(i.e., to minimize acceleration errors) the gain of the

error-processor integrator, and the sensitivity of the

VCO it drives, should both be high. This encourages

"hunting" or "jitter" around the null (zero-error) point,

due primarily to quantizing "noise." It is for this rea-

son that a small (one bit) hysteresisthreshold is built

into the error processor. This threshold is much

smaller than the rated angular error.

Several other functions generally incorporated into

modern S/D or R/D converters to make them more

versatile are loss of signal(LOS) and enable(EL and

EM). LOS is used for system safety and as a diag-

nostic testing point.It is generated by monitoring the

input signals. Loss of both the sine and cosine sig-

nals at the same time will trigger the LOS flag.The

enable (EL and EM) line(s) enable the output buffers,

usually in two 8-bit bytes for use with either 8- or 16-

bit buses.

Because the tracking converter configuration of

Figure 2.1 is the most advanced and versatile device

of its kind in use today, we shall examine and analyze

its static and dynamic performance in more detail ...

principally in Section VII.

THEORY OF OPERATION OF MODERN

S/D AND R/D CONVERTERS

RESOLUTION

Input Frequency

Tracking Rate

Bandwidth

acc-1 LSB lag

Settling Time

PARAMETER

BITS

Hertz

RPS min.

Hertz

1/sec2nominal

1/sec nominal

deg/sec2nominal

ms max.

UNITS

360 - 1000

160

2.5

220

81.2k

12.5k

2.0

0.31

40k

285

112

28.4k

7.1k

275

160

300

800

400 HZ

47 - 1000

2.5

0.61

780

0.29

0.078

10k

264

17.2

4.3

350

550

1400

3400

60 HZ

BANDWIDTH

Table 2.1.Dynamic Characteristics

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THEORY OF OPERATION OF MODERN

S/D AND R/D CONVERTERS

Briefly though, the dynamic performance of the

Type II tracking convertercan be determined from

its transfer functionblock diagram (shown in Figure

2.2) and open- and closed-loop Bode plots (shown

in Figures 2.3 and 2.4).

Table 2.1 lists the parameters and dynamic characteris-

tics relating to one of DDC's leadership converters, the

SDC-14560 series. The values of the variables in the

transfer function equation are given on the applicable

data sheet. All DDC's tracking synchro-to-digital or

resolver-to-digital converters are critically damped and

have a typical small signal step response (100 LSB

step) as shown in Figure 2.5. Large signal step

responseis governed by the maximum tracking rate of

ERROR PROCESSOR

RESOLVER

INPUT

CONVERTER TRANSFER FUNCTION G =

WHERE:

A = A A

1 2

VELOCITY

OUT

DIGITAL

POSITION

OUT

(φ)

VCO

A + 1

S + 1

10B

H = 1

A + 1

S + 1

10B

2 2 A

ω (rad/sec)

CLOSED LOOP BW (Hz) =

2 A

-12 db/oct

-6 db/oct

10B

ω (rad/sec)

Figure 2.2.Transfer FunctionBlock Diagram.

Figure 2.3.Open-Loop Bode Plot.

Figure 2.4.Closed-Loop Bode Plot.

the converter and the small signal settling time. A typi-

cal response is shown in Figure 2.6. In the newer

designs, such as the RDC-19220 series, bandwidthcan

be selected to suit the particular application. A good rule

to follow is to keep the carrier frequency four times the

bandwidth. As the bandwidth becomes a larger per-

centage of the carrier it will become progressively more

jittery until at the extreme it will attempt to follow the car-

rier rather than the carrier envelope.

Use of a "Synthesized" Reference

As the error analysis (see Sections VII and VIII) of

the synchro-to-digital converter of Figure 2.1 will

show, one potentially significant source of error is

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THEORY OF OPERATION OF MODERN

S/D AND R/D CONVERTERS

100

Output (LSBs)

Time (ms)

LOW BANDWIDTH - 10-BIT MODE

100

Output (LSBs)

Time (ms)

LOW BANDWIDTH - 12-BIT MODE

100

Output (LSBs)

Time (ms)

LOW BANDWIDTH - 14-BIT MODE

100

Output (LSBs)

Time (ms)

LOW BANDWIDTH - 16-BIT MODE

Figure 2.5.Small Signal Step Response (100 LSB Step).

100

Output (LSBs)

Time (ms)

HIGH BANDWIDTH - 10-BIT MODE

100

Output (LSBs)

Time (ms)

HIGH BANDWIDTH - 12-BIT MODE

100

Output (LSBs)

Time (ms)

HIGH BANDWIDTH - 14-BIT MODE

100

Output (LSBs)

Time (ms)

HIGH BANDWIDTH - 16-BIT MODE

THEORY OF OPERATION OF MODERN

S/D AND R/D CONVERTERS

120

180

Output Angle (degrees)

Time (ms)

LOW BANDWIDTH - 10-BIT MODE

120

180

Output Angle (degrees)

Time (ms)

LOW BANDWIDTH - 12-BIT MODE

120

180

100

Output Angle (degrees)

Time (ms)

LOW BANDWIDTH - 14-BIT MODE

120

180

100

Output Angle (degrees)

Time (ms)

LOW BANDWIDTH - 16-BIT MODE

120

180

Output Angle (degrees)

Time (ms)

HIGH BANDWIDTH - 10-BIT MODE

120

180

Output Angle (degrees)

Time (ms)

HIGH BANDWIDTH - 12-BIT MODE

120

180

Output Angle (degrees)

Time (ms)

HIGH BANDWIDTH - 14-BIT MODE

120

180

100

Output Angle (degrees)

Time (ms)

HIGH BANDWIDTH - 16-BIT MODE

Figure 2.6.Large Signal Step Response (179° Step).

time phase shift (typically, a phase lead between the

rotor excitation reference signal and the voltages

induced in the stator windings of the synchro or

resolver). This can cause errors due to the fact that

the voltage applied to the rotor is also used as the

reference input to the phase-sensitive demodulator.

Any appreciable lag or lead between this reference

voltage and the modulated carrier will greatly reduce

the ability of the demodulator to reject quadrature of

the synchro-input signals. (The sources of quadra-

ture components are discussed Section VIII, but pri-

marily they comprise speed voltages induced into the

synchro or the resolver stator and differential static

phase shift from the rotor to each stator output.)

Although a first order correction can be made for

rotor/stator reference phase shift by introducing a

phase-advancing network (Figure 2.7) between the

reference input and the demodulator, this phase cor-

rection can only be approximate, since the nominal

phase lead of a particular synchro or resolver design

is not a tightly controlled parameter, and varies from

synchro to synchro, and also with temperature, load-

ing, etc. Trimming the phase-correction network for a

particular synchro is practical, if somewhat inconve-

nient. A much better solution to the problem of ref-

erence phase errors is the use of "synthesized refer-

ence." A synthesized reference is a reference volt-

age that is derived directly from the stator-generated

signals (or from their Scott-T-transformed resolver-

format resultants). This technique is illustrated in

Figure 2.8.

Before proceeding to a description of the reference

synthesizer it should be said that it is necessary to

generate a precise reference only in conversion sys-

tems and instruments that require better than 1

minute accuracy ... or in conversion systems or

instruments that must operate in several modes hav-

ing different phaseshifts.

THEORY OF OPERATION OF MODERN

S/D AND R/D CONVERTERS

SCOTT T

TRANSFORMER

SYNCHRO

INPUT

B SIN θ COS (ωt + α)

B COS θ COS (ωt + α)

SYNTHESIZED

REFERENCE

K COS (ωt + α )

PHASE

COMPARATOR

REFERENCE GENERATOR

QUADRANT SELECTOR

EXTERNAL

REFERENCE

INPUT

A COS (ωt )

PHASE-LEAD

NETWORK

(+α)

REFERENCE

INPUT

CONVERTER

f (cos ωt - α)

REFERENCE

VOLTAGE

FROM

SYSTEM

f (cos ωt)

Figure 2.8.Method of Synthesizing a Reference Carrier without PhaseError.

Figure 2.7.Phase-Advancing Network.

In Figure 2.8, we see a system in which a reference

synthesizer (or "reference generator," as it is some-

times called) receives three inputs:

1.The external reference, a carrier frequency signal

of essentially constant amplitude:A cos (ωt).

2.The sin θ output of the quadrant selector circuit

that is part of the tracking servo of Figure 2.1:

B sinθcos (ωt+α). Note that is the carrier phase-

lead error between the external reference signal

and the stator input signals.

3.The cosθoutput of the quadrant selector circuit of

Figure 2.1, which has the same phase-lead

error:

B cosθ cos(ωt+α).

Inputs 2 and 3, which are always of opposite polari-

ty, are subtracted algebraically into a single carrier

signal, and amplitude leveled. This signal can be

shown to be either K cos (ωt+α) or K cos

(ωt+α+180°), where K is a constant ...either in phase

or 180° out of phase with the desired reference, and

corrected for the carrier-phase-lead error. By com-

paring it with the external reference, in a "coarse"

phase comparator (which merely determines

whether or not it is within ±90° of the external refer-

ence), the logical decision is made between closing

S1 (using the leveled algebraic sum), or closing S2

(inverting the leveled algebraic sum). The output of

S1 or S2 is, then, the synthesized reference.

The time phase of the synthesized reference signal

can be dependably held to within ±5 minutes of the

sin (θ - φ) signal presented to the demodulator, since

phaseshifts in the multipliers and differencing circuit

are very small at the carrier frequency. This level of

time-phase coherence ensures optimum quadrature

rejection in the demodulator ..at least 200:1, and as

much as 2000:1 in special designs.

The error introduced by a nominal 5.7° phase shift

and 0.1% quadrature in a converter without a syn-

thesized reference is approximately:

While in a converter with a synthesized reference the

5.7° phase shift is effectively reduced to 5 minutes

(or 0.01°) and the error is approximately:

A very small number indeed.

The use of a synthesized reference allows an engi-

neer to use the same circuit card or system design in

various applications without being concerned about

the phase shifts of the various synchro or resolver

transducers used.

Sampling A/D Converters

The tracking converter described first in this section

is a very high-performance device, and is the logical

choice for many applications; however, there are

other methods of digitizing the input data represent-

ing the angle θ, and at least two of them are worth

detailed study. Both take advantage of the fact that

all the data needed to determine the angle θ is

known in the carrier-envelope amplitudes of the two

resolver-format inputsat one selected instant of time

during the carrier cycle, provided that they are mea-

sured simultaneously ... assuming appropriate scal-

ing. Thus,if the reference input is:

Vref = K

cos (ωt), after correction for rotor-stator

phase shift, and the two resolver-format inputs are:

Vx = K

sinθcos(ωt);

and Vy = K

cosθ cos(ωt),

then simultaneous samples of Vx and Vy will yield as

much information about sinθand cosθas would con-

tinuous observation.

The only essential requirement of this approach is to

read Vx and Vy simultaneously—we must measure

Eq = tan 0.01˚ = 0.006'

0.1

100

Eq = tan 5.7˚ = 0.34'

0.1

100

THEORY OF OPERATION OF MODERN

S/D AND R/D CONVERTERS

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