83
The error processor comprises only two elements: a
comparator, which senses the polarity of the input
signal, sin (θ - φ); and a gated clock-pulse generator,
which produces an output pulse whenever sin (θ - φ)
is positive - i.e., whenever θ is greater than φ. Thus,
as long as θ exceeds φ, the error processor will feed
clock pulses to the register.
The complete S/D conversion procedure may now be
described as follows. First, assume that the register
has been cleared i.e., preset to all ZEROES, either
by the internal programming logic or by external
command, before the peak of the reference carrier
initiates its sample command. Then, the resolver-for-
mat outputs of the Scott-T synchro isolation trans-
former are sampled simultaneously, at the carrier
peak, by a circuit of the type shown in Figure 2.9.
The resultant DC levels are presented to the SSCT,
and sin (θ - φ) is computed.
At this point, all of the bits stored in the "n"-bit regis-
ter - i.e., all of the bits of the output word - are at
ZERO; so that the digital word presented to the sine
and cosine multipliers (as the angle φ) is a set of "n"
ZEROES.
Now begins a sequence of n logical "decisions,"
each of which follows the pattern of the first one. The
first three decisions will be described in detail:
(1) The most-significant bit of the register is set to
ONE, so that the word φ fed to the sine and
cosine multipliers is 1000...0, corresponding to
φ=180°.
(2) The error processor is then "interrogated" - that
is, its output is examined. Now, if θ is larger than
180°, the value of sin (θ - φ) will be positive, and
the error processor will produce a ONE. The ONE
will allow the first stage (most significant bit) of the
output register to remain at the ONE state. If θ is
less than 180°, the error processor will not put out
a ONE, but a ZERO state ...which it should be, for
θ< 180°.
(3) The first decision has now been reached, and
the logic automatically proceeds to the next deci-
sion...that concerning the correct state for the sec-
ond most-significant bit (second stage of the reg-
ister).
(4) The second stage is set to ONE, so that the out-
put word is either 11000...0 (for θ > 180° in deci-
sion #1) or 01000...0 (for θ > 180° in decision #1.)
(5) Again, the error processor is interrogated. Since
decision #1 had two possible results, we shall
consider both.
(a) If θ is greater than 180°, the value of φ at this
interrogation is 11000...0, or 270°. Thus, if θ lies
between 270° and 360°, the second decision will
be to leave the second register stage in the ONE
state; and if θ lies between 180° and 270°, the
THEORY OF OPERATION OF MODERN
S/D AND R/D CONVERTERS
28
Vx
Vy
SAMPLING
CIRCUIT
(SEE FIG. 2.9)
θ
IN
SSCT
SEQUENTIAL ADDRESS LOGIC
REGISTER
QUADRANT
SELECTOR
SINE
MULTIPLIER
COSINE
MULTIPLIER
SIN(θ - φ)
180
90
CLOCK PULSES
DIGITAL
OUTPUT
ERROR
PROCESSOR
Figure 2.10. Successive-Approximation S/D Converter.
116
second decision will be to return the second stage
to the ZERO state.
(b) If θ is not greater than 180°, the value of φ at this
interrogation is 01000...0, or 90°. Thus, if θ lies
between 90° and 180°, the second decision will be
to leave the second register stage in the ONE
state;and if θ lies between 0° and 90°, the second
register stage will be returned to the ZERO state.
(6) Now, the decision-making process moves to the
third register stage, into which a ONE is intro-
duced...and the process continues. Note that this
third decision will have a "weight" of 45°, whereas
the second decision added or subtracted a possi-
ble 90°, and the first decision was the "largest
weight"...corresponding to ±180°.
The process described above continues through a
total of "n" decisions, each one causing the digital
output angle word to come closer to the exact value
of θ - "successively approximating" θ; hence the
name successive-approximation converter. The last
decision has the weight:
...and leaves the final result with ±1/2 LSB uncer-
tainty. For example, for n = 13, 2² = 8,192, and the
"quantization uncertainty" of the result is 360°/ 8192,
or ±2.6 minutes. The resolution of the converter,
then, is ±2.6 minutes, or about ±0.044 degrees.
The entire conversion process requires very little
time - indeed, if every carrier peak is to be sampled
and converted, the conversion must be completed in
less than one carrier period. Modern high-speed
converters are so fast that hundreds of complete,
high-resolution conversions can be done in one car-
rier period ... a fact that becomes important when
multiplexed systems are considered, later in this sec-
tion.
Despite this high conversion speed, the successive-
approximation converter can suffer from a "stale-
ness" error, due to the fact that the data determining
Least Significant Bit =
n
360˚
2
θare sampled only once per carrier period. If θ is
changing, a periodically varying velocity error will
result.This error is reduced almost to zero immedi-
ately after each new sample updates the register,
and thereafter increases to a maximum of:
for constant velocity between samples.
The SamplingHarmonic Oscillator Synchro-to-
Digital Converter
The second type of sampling S/D converter that we
shall examine is illustrated in Figure 2.11. Although
not in common use anymore, it is discussed here for
historical purposes. Note that the sampling tech-
nique used in the converter is somewhat different
from that used in the sampling successive-approxi-
mation converter of Figure 2.10, in that the resolver-
format input signals are first fed to phase-sensitive
demodulators, the outputs of which are DC levels:
Vx = K sin θ
Vy = K cos θ
Velocity Error
(in degrees)
Velocity (in )
carrier frequency (in Hertz)
degrees
second
=
THEORY OF OPERATION OF MODERN
S/D AND R/D CONVERTERS
29
SCOTT
"T"
XFMR
SYNCHRO
INPUTS
SIGNALS
Vref
INPUT
STROBE
INPUT
STROBE
PHASE
SENSITIVE
DEMOD'R
PHASE
SENSITIVE
DEMOD'R
S/H
S/H
S1
S1
S2
S2
Vy
Vy
Vx
R1
R2
R
R
C1
C2
CLOCK
PULSE
GENERATOR
CONTROL
LOGIC
DIGITAL
COUNTER
GATE
DIGITAL OUTPUT
A
Vx
Figure 2.11.Sampling Harmonic Oscillator S/D
Converter.
128
where K is a constant and θ is the shaft angle to be
digitized. It is these DC levels that are sampled at
the appropriate time, to set the initial conditions of
the integrators in a harmonic oscillator converter.
The remainder of the circuit comprises two main sec-
tions:
(1) A two-integrator-plus-inverter chain, enclosed in
a positive-feedback loop. This loop, if "unclamped"
(by appropriate programming of the electronic
switches S1 and S2), will oscillate at a frequency
determined solely in the integrator time constants.
(2) A clock-pulse generator/digital-counter circuit that
can be gated on when the oscillator is unclamped,
and gated off at the positive-going zero-crossing of
the voltage at point "A" in Figure 2.11.
Initially, however, the loop is clamped, and prevented
from oscillating by the closure of the electronic
switches S1 and S2 which apply the sampled DC lev-
els, Vx and Vy, as initial conditions to the two inte-
grators. When the integrators have stabilized at
these initial conditions, the switches are opened, the
oscillation begins (see Figure 2.12) and, simultane-
ously, clock pulses are gated into the counter. When
the positive-going zero crossing is reached (point "X"
in Figure 2.12), the clock pulses are inhibited, and
counting stops. At that point, the total stored in the
counter is the digitized value of θ, the shaft
angle...provided only that the clock frequency bears
the correct relationship to the integrator time con-
stants. The proof of this relationship between θ and
the stored count, for the initial conditions described,
is given below.
The voltage at point A can be shown to bear the fol-
lowing relationship to the initial conditions:
If the integrator time constants are equal, and the
inverter gain is unity, the natural loop-oscillation fre-
quency, f
L
, is given by:
Note that if the time constants are not equal, the nat-
ural frequency is:
where Ai is the gain of the inverter. Referring now to
the waveform of Figure 2.12, we see that at point
"X", the positive zero crossing that stops the count-
ing process, the following relationships hold:
sin
(
-
)
= 0
2πθ
360˚
t
RC
or
2πθ
360˚
t
RC
=
2π
R
,
C
,
R
,
C
,
A
1
1
1
2
2
i
so that V = sin
(
-
)
2πθ
360˚
A
f =
1
2πRC
L
from which ω =
1
RC
L
t
RC
V = sin
(
ω t -
)
2πθ
360˚
L
A
where ω = 2πf
L
L
f = the natural oscillation frequency
of the loop,
L
t = the time, in seconds, measured from
the moment of unclamping,
and θ = the input angle to be digitized, in
degrees.
THEORY OF OPERATION OF MODERN
S/D AND R/D CONVERTERS
30
X
360
θRC
RC
START
STOPS
COUNTING
Va
V
X
(INITIAL
CONDITION)
t = 0
Figure 2.12.Timing Diagram for Figure 2.11.
85
Clearly, then, if the clock rate is proportioned so that
some convenient number of pulses - say, 3600 - are
produced in 2πRC seconds, the count at point "X"
will be:
and the total stored in the counter will represent the
angle θ to a resolution of 0.1°, or 1 part in 3600. Any
desired resolution may be obtained (within the stabil-
ity and accuracy limits discussed below) by selecting
the appropriate clock frequency - usually some deci-
mal multiple of 360. Although it is easy and relative-
ly inexpensive to stabilize the frequency of a clock-
pulse generator, it is not easy to stabilize the RC time
constants of the integrators, and it is the ratio of the
clock frequency to the integrator time constants that
determines the attainable accuracy and meaningful
resolution ... ignoring all other sources of error. It is
this stability problem which has caused this tech-
nique to be abandoned by most manufacturers.
In the most advanced harmonic oscillator designs, a
phase-locked-loop clock generator is used to force
the clock frequency to track the unavoidable drift
integrator time-constant (and to compensate for
other error sources, as well), so that meaningful
overall accuracy can be achieved. The best worst-
3600
360
(θ)
case "static" error for this class of designs is ±6 min-
utes at considerable cost and complexity.
In Section III, the use of the harmonic oscillator for
synchro/DC and synchro/sine-cosine conversion will
be discussed.
Multiplexing Synchro-to-Digital Converters
Either of the two sampling S/D converters previously
described can be "shared" by a group of synchros or
resolvers, so that more than one source of input data
(i.e., more than one shaft angle) can be digitized by
the same converter circuitry, with a consequent sav-
ings, not only of initial equipment cost, but also of
required power-supply energy, space, and weight. In
addition, reliability is greatly enhanced, by reduction
in component count. Some additional circuitry is
always required, at least to perform the multiplexing
(switching) of the converter from sensor to sensor,
and some systems require the use of a separate set
of sample-hold circuits for each data input, as we
shall see. Consequently, the use of multiplexing is
less attractive for only two or three input sensors
than it is for many more.
In the simplest approach to sharing an S/D convert-
er (see Figure 2.13), the pair of sample-hold circuits
shown in Figure 2.9 are successively switched from
THEORY OF OPERATION OF MODERN
S/D AND R/D CONVERTERS
31
θ
1
θ
2
θ
n
SCOTT
T
SCOTT
T
SCOTT
T
MUX
ADDRESS
INPUT
MULTIPLEXER
DUAL S/H
CIRCUIT
AS IN
FIGURE 2.9
S/D
CONVERTER
STROBE
INPUT
DIGITAL
OUTPUT
CHANNEL "N"
CHANNEL 1
CHANNEL 2
Figure 2.13. Multiplexed-Sample/Hold (Sequential Sampling) Approach to Sharing an S/D Converter.
90
input to input, sampling each, holding the value dur-
ing conversion (which takes considerably less time
than one carrier cycle), and then sampling the next at
the peak of the next succeeding carrier cycle.
This scheme has the advantage of simplicity and
economy, since all that is added in the way of hard-
ware is a multiplexer module and one input isolation
module (synchro or resolver) per input sensor. The
disadvantage of successive-peak sampling is the
fact that it compounds the "staleness error" men-
tioned on page 28, by making each successive read-
ing one full carrier period later than the preceding
one; therefore, in multiplexing n inputs, the possible
"skew error", as it is called, between readings of the
first and the n
th
channels (as well as between two
successive readings of any channel) is n times the
possible skew error (due to staleness) of a convert-
er-per-channel system.
(There are some second-order advantages and dis-
advantages of the sequential-on-successive-peak
multiplexed approach to time-sharing a converter,
but they will be discussed later sections).
For data-acquisition systems in which the velocity of
one or more of the input channels is high, and for all
systems in which optimum accuracy is essential, a
much better technique for time-sharing the converter
is that shown in Figure 2.14 - the simultaneous-sam-
ple-and-hold approach. In this scheme, each input
sensor is equipped with its own pair of sample-holds,
and all sample-holds are strobed (activated) at the
same instant ... at carrier peak, as before. The mul-
tiplexer then switches the converter (only) from one
pair of "frozen" sine/cosine inputs to the next, paus-
ing at each input channel only long enough to digi-
tize the shaft-angle data and store or report it. If the
converter and multiplexer are fast enough, many
channels can thus be scanned and converted in a
single carrier cycle, thereby freeing the sample-
holds for simultaneous sampling of the very next car-
rier peak, thus minimizing the possible staleness
error to the single carrier-period value attained by
the circuits of Figures 2.10 and 2.11. Regardless of
scanning speed, however, the data sampled, held,
converted, and reported in a single pass is essen-
tially free of channel-to-channel skew, although it will
soon be "out of date" (stale).
Here again, there are many second-order effects to
consider, but they will merely be mentioned briefly
now, and considered in more detail in later sections:
• A possible source of skew is the aperture-time
uncertainty among the various sample-holds.
THEORY OF OPERATION OF MODERN
S/D AND R/D CONVERTERS
32
CHANNEL 1
CHANNEL 2
CHANNEL "N"
θ
1
θ
2
θ
n
SCOTT
T
SCOTT
T
SCOTT
T
S/H
S/H
S/H
S/D
CONVERTER
STROBE
INPUT
M
U
L
T
I
P
L
E
X
E
R
Figure 2.14.Simultaneous-Sample/Hold (Sequential Sampling) Approach to Sharing an S/D Converter.
111
This is the uncertainty (often called "jitter") in the
interval between the application of the hold com-
mand and the actual "freezing" of the signal.
• The input/output (or transfer) gain of the sample-
holds may vary slightly, creating an error.
• The hold circuits have a finite "droop rate," caused
by switch leakage in the sample-hold circuit.
Note that all the above effects have the potential of
causing error even in single channel systems,
because they can create differences between the
sine and cosine sample obtained by a single pair of
sample-holds. Fortunately, modern high-perfor-
mance sample-holds are available that render all of
the above effects negligible, except in the most pre-
cise systems .. and even then, they can be mini-
mized.
The individual multiplexer channels must be subject-
ed to the same scrutiny. They, too, have settling time
and transfer-gain uncertainties, and can contribute
errors. And the isolation transformers do not all have
exactly the same time phase shifts, either. All of
these uncertainties, however, yield to the use of the
more advanced, modern hardware, and can almost
always be rendered negligible.
Finally, one must recognize that there is an error
source that cannot be controlled by the design of the
synchro-to-digital sampling/multiplexing/conversion
system: the random variation in rotor-to-stator time-
phase-shift in the sensors themselves. First-order
correction of these uncertainties is discussed later,
but they are always a final limitation on all multichan-
nel systems.
In the "addressing" of the multiplexer - i.e., the
means by which it is commanded to switch from
channel to channel - it is important to note that the
scanning of a set of channels need not be sequen-
tial. The multiplexer may be commanded to select
channels in any order. This capability is called "ran-
dom" scanning, and may take many forms - arbitrary
sequences that have no predictable pattern but
respond instead to a computer's reactive behavior;or
deliberate "skipping" of certain channels in a
sequence on certain passes;or attenuated-scan/full-
scan programs, in which some channels are exam-
ined in every pass, some in every tenth pass, etc.
Synchro- or Resolver-To-Digital Converters for
Two-Speed Systems
Earlier, on page 11, the characteristics of two-speed
synchros for very high-resolution applications were
THEORY OF OPERATION OF MODERN
S/D AND R/D CONVERTERS
33
QUADRANT
SELECTOR
FUNCTION
GENERATOR
ISOLATION
XFMR
(FINE)
ERROR
PROCESSOR
UP-DOWN COUNTER
QUADRANT
SELECTOR
ISOLATION
XFMR
(COARSE)
DIGITAL
MULTIPLIER
S1
S2
S3
S1
S2
S3
RH
RL
FINE
ERROR
COARSE
ERROR
CROSS-OVER
DETECTOR
INH
CB
DIGITAL
OUTPUT
sin
sin
sin
cos
cos
cos
F
G
H
D
E
1
16
A
B
C
COARSE
SYNCHRO
FINE
SYNCHRO
FUNCTION
GENERATOR
I
Figure 2.15.Two-Speed S/D Converter.
68
introduced. Typical converter circuitry for digitizing
two-speed inputs is shown in Figure 2.15. Note its
similarity to the basic single-speed tracking convert-
er of Figure 2.1. In fact, if one considers only circuit
blocks A through E, the "coarse" converter, the cir-
cuits are identical. The "fine" converter feeds circuit
blocks F, G, and H, and shares blocks I, D, and E, the
error processor, cross-over detector and switching
circuit and the up-down counter, with the coarse-syn-
chro converter.
Each of the two sets of circuit blocks described
above constitutes, in itself, a single-speed tracking
converter. The only difference between them is that
the coarse loop has much lower resolution - i.e.,
fewer "bits". The fine-synchro converter provides the
additional resolution required by the application. The
number of bits provided by the coarse converter is
determined by the speed ratio, and is always at least
a fraction of a bit higher than the value of Nc, calcu-
lated from:
Where Nc is the resolution of the coarse-synchro
converter, and Vf/Vc is the speed ratio of the syn-
chros.
Circuit block I, the crossover detector, monitors the
sin (θ - φ) error signal produced at the differencing
junction following the sine/cosine multipliers of the
1
N
2
90˚ of the fine synchro
V /V
≤
f
c
c
THEORY OF OPERATION OF MODERN
S/D AND R/D CONVERTERS
34
COARSE
GEAR
FINE
GEAR
TRANSDUCER
DIGITAL
DATA
DIGITAL
PROCESSOR
OR
TWO-SPEED
R/D
CONVERTER
M
1
18
Figure 2.16.Microprocessor Combining of Two-Speed Data.
R/D
R/D
FINE
COARSE
TWO-
SPEED
COMBINER
RESULTANT
ANGLE
SD-15900
nx
1x
Figure 2.17.Two-Speed Resolvers.
98
coarse converter, and, when that error signal falls
below approximately 90° of the fine converter it gates
the error signal of the fine converter into the error
processor.
It is important to note that the sine/cosine multipliers
of both converters are simultaneously presented with
the digital state of the up-down counter ... so that
when the coarse-to-fine crossover occurs, the transi-
tion is smooth, and the tracking continues without
significant discontinuity. Anytime the coarse-convert-
er error signal exceeds the crossover threshold of
the coarse converter, the crossover detector switch-
es the error processor back to the error signal pro-
duced by the coarse converter.
Although it may not be immediately obvious, it is true
that the behavior of this two-speed tracking convert-
er is exactly the same as that of the single-speed
tracking converter. Both are true Type II closed-loop
servos; both are free of velocity error, and both pre-
sent information that is always "fresh."
Hardware Combining of Two-Speed Data
With the advent of low-cost single-speed tracking
R/Ds and microprocessors being used in most sys-
tems, many engineers are using the microprocessor
to do the combining where two-speed configurations
are necessary. Figure 2.16 is a diagram of such a
system. In place of a microprocessor, DDC has
developed a two-speed combining circuit (see Figure
2.17), the SD-15900, that will control the digital data
from two single-channel R/D converters (i.e., RDC-
19220 series) or a two-channel S/D or R/D hybrid
(i.e., SD-14620 series) and produce one digital word.
The combiner is available in two types: one to com-
bine a 1:36 system and the other is programmable
for 1:4, 1:8, 1:16, 1:32, and 1:64 systems.
The main advantages of using this approach are cost
and flexibility. Two-speed S/Ds, because they are
built in relatively small numbers, are costly and
restricted to 1:36 (except on special order) speed
ratios. With microprocessor combining of the data
from two single-speed converters, nonstandard
speed ratios may be used and even changed from
system to system under software control.
The biggest disadvantage of using this approach is
that the velocity of the fine-speed shaft is limited to
the tracking rate of the converter used whereas in the
crossover detector method it is the coarse-speed
shaft velocity that is limited to the tracking rate of the
converter. Thus the microprocessor combining
method has a 1/n (n=speed ratio) tracking rate limi-
tation compared to the crossover detector method.
The algorithm for combining the two single-speed
data words is to use the fine-speed data for accura-
THEORY OF OPERATION OF MODERN
S/D AND R/D CONVERTERS
35
+15 +5
-15 GND
S1
S2
S3
S1
S2
S3
S1
S2
S3
RH
RH
RH
RH
RL
RL
RL
RL
SYNCHRO
SIMULATOR
SIM 31200
CX WITH
VERNIER
S/D
CONVERTER
MSB
LSB
LAMP &
DRIVER
LAMP &
DRIVER
TO
OR
REFERENCE
SR 203
SYNCHRO ANGLE
INDICATOR
(a)
(b)
(c)
Figure 2.18.Test Configurations, Single-Channel Tracking and Sampling Converters.
210
36
THEORY OF OPERATION OF MODERN
S/D AND R/D CONVERTERS
cy and the coarse-speed data for turns counting.
Since it is impossible to have the two synchros exact-
ly aligned it is necessary to correct the coarse-speed
data word (since it is used only to know which turn
the fine synchro is on). This can be done by taking
the coarse speed data and multiplying it by the
speed ratio n and doing an ambiguity analysis by
comparing the two MSBs of the fine data to the
appropriate two bits of the coarse data. If they are
equal then the coarse data is correct. If the fine data
is 1 LSB larger than the coarse data then add 1 LSB
to the coarse. If the fine data is 1 LSB smaller than
the coarse then subtract 1 LSB from the coarse data.
If the difference is greater than 1 LSB then the sys-
tem is out of sync and the synchros or resolvers must
be mechanically realigned. Once the data has been
corrected, discard the coarse data not needed to
simply count turns, and take the combined data word
and divide by the speed ratio n for the output data
word. If the speed ratios happen to be binary the
multiplication and divisions are trivial.
Testing S/D Converters
Testing or evaluating a synchro-to-digital or resolver-
to-digital converter will generally require a synchro
standard (a calibrated synchro with an accurate dial or
a synchro/resolver simulator), an interconnection box
or fixture, and LED bank or Digital Voltmeter (DVM).
Single Channel S/D or R/D Converter
Figure 2.18 illustrates configurations to test static
accuracy on single-channel tracking or sampling
converters. A LED driver or suitable readout is nec-
essary for each of the data outputs. (The circuit
shown in Figure 7.7, is recommended.) The syn-
chro/resolver standard is set to the test angles. The
angles corresponding to the LEDs that are on are
added and compared with the standard angle.Table
2.2 shows the relationship of angles vs. bits.
A typical room temperature error curve is shown in
Figure 2.19. Each quadrant is identical; the error
shown is for the first quadrant. Error limits are also
indicated for temperature extremes.
Multiplexed S/D Converters
Figure 2.20 illustrates the test setup for multiplexed
S/D converters. It requires, in addition to power sup-
plies, an accurate source of synchro or resolver sig-
2
N
LSB AS % OF
FULL SCALE
DEGREES
PER BIT
MINUTES
PER BIT
SECONDS
PER BIT
RADIANS
PER BIT
RESOLUTION
N IN BITS
1
2
4
8
16
32
64
128
256
512
1,024
2,048
4,096
8,192
16,384
32,768
65,536
131,072
262,144
524,288
1,048,576
100.
50.
25.
12.5
6.25
3.125
1.5625
.78125
.390625
.1953125
.09765625
.04882813
.02441406
.01220703
.00610352
.00305176
.00152588
.00076294
.00038147
.00019074
.00009537
360.
180.
90.
45.
22.5
11.25
5.625
2.8125
1.40625
.703125
.3515625
.1757813
.0878906
.0439453
.0219727
.0109863
.0054932
.0027466
.0013733
.0006866
.0003433
21,600.
10,800.
5,400.
2,700.
1,350.
675.
337.5
168.75
84.375
42.1875
21.09375
10.54688
5.27344
2.63682
1.31836
.65918
.32959
.16479
.08240
.04120
.02060
296,000.
648,000.
324,000.
162,000.
81,000.
40,500.
20,250.
10,125.
5,062.5
2,531.25
1,265.6250
632.8125
316.4063
158.2031
79.1016
39.5508
19.7754
9.8877
4.9438
2.4719
1.2360
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
6.28318531
3.14159265
1.57079633
.78539816
.39269908
.19634954
.09817477
.04908739
.02454369
.01227185
.00613592
.00306796
.00153398
.00076699
.00038350
.00019175
.00009587
.00004794
.00002397
.00001199
.00000599
Table 2.2. Binary Angle Relationships
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